Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Document Table of Contents

6.1. Preparing the Board

Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears and allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.

The Board Test System shares the JTAG bus with other applications like the Nios® II debugger and the Signal Tap Embedded Logic Analyzer. Because the Intel® Quartus® Prime Programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Intel® Quartus® Prime Programmer.

With the power to the board OFF, following these steps:

  1. Connect the USB cable to the board.
    If you connect an external USB-Blaster download cable and power cycle the board, the on-board Blaster is disabled. To successfully use the USB-Blaster cable, disconnect it before power cycling the board. After you power cycled the board, then reconnect the USB-Blaster cable.
  2. Ensure that the development board DIP switches are set to the default positions as shown in the “Factory Default Switch Settings”.
    To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. The application cannot run correctly unless the USB cable is attached.