Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Document Table of Contents

5.6. Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:
  • JTAG Chain Device Removal Switch
  • Program Select Push Button
  • MAX V Reset Push Button
  • CPU Reset Push Button

JTAG Chain Device Removal Switch: The JTAG chain will connect the Intel® Arria® 10 GX FPGA and the MAX V CPLD devices in a chain, with the option to selectively bypass the MAX V CPLD by a dip switch setting. This switch will be one position of a 6-position switch. The other positions will consist of the MSEL bits for configuration modes, Fan Control and VID enable.

Program Select Push Button: After a POWER-ON or RESET (reconfiguration) event, the MAX V will configure the Intel® Arria® 10 GX FPGA in FPP mode with either the FACTORY POF or a USER defined POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this button and observing the program LEDs (FACTORY or USER) dictates which program will be selected. Then the PGM_CONFIG pushbutton needs to be pressed to load the program.

MAX V RESET Push Button: This pushbutton is the board Master Reset. This button is connected to the MAX V CPLD (MAX_RESETn pin) that is used for FPP configuration. When this button is pressed, the MAX V CPLD will initiate a reloading of the stored image from flash memory using FPP configuration mode. The image that is reloaded depends on the PGMSEL setting.

CPU RESET Push Button:This pushbutton is the Nios® II CPU Reset. This button is connected to an Intel® Arria® 10 GX FPGA DEV_CLRn and can be used by Nios® II implementations as a dedicated CPU Reset button. This button is also connected to the MAX® V CPLD so that the FPGA device can be reset right after its configuration with FPP mode.