Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 12/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide A. Programming the Flash Memory Device B. Safety and Regulatory Compliance Information
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Installing the Quartus® Prime Software 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria® 10 FPGA 5.3. MAX® V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria® 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External Intel® FPGA Download Cable
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded Intel® FPGA Download Cable Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitor 6.4.9. Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX® V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. XCVR1 Tab—Status 6.4.5.2. XCVR1 Tab—Port 6.4.5.3. XCVR1 Tab—PMA Setting 6.4.5.4. XCVR1 Tab—Data Type 6.4.5.5. XCVR1 Tab—Error Control 6.4.5.6. XCVR1 Tab—Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. XCVR2 Tab—Status 6.4.6.2. XCVR2 Tab—Port 6.4.6.3. XCVR2 Tab—PMA Setting 6.4.6.4. XCVR2 Tab—Data Type 6.4.6.5. XCVR2 Tab—Error Control 6.4.6.6. XCVR2 Tab—Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. XCVR3 Tab—Status 6.4.7.2. XCVR3 Tab—Port 6.4.7.3. XCVR3 Tab—PMA Setting 6.4.7.4. XCVR3 Tab—Data Type 6.4.7.5. XCVR3 Tab—Error Control 6.4.7.6. XCVR3 Tab—Run Control
6.4.9. Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX® V CPLD to the Factory Settings
B. Safety and Regulatory Compliance Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide
A. Programming the Flash Memory Device
B. Safety and Regulatory Compliance Information

5.11. Flash Memory

The Arria® 10 GX transceiver signal integrity development board has two 1-Gbit CFI compatible synchronous flash device for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

Two flash devices are implemented to achieve a 32-bit wide data bus at 16 bits each per device. The target device is a Micron PC28F00AP30BF CFI Flash device. Both MAX V CPLD and Arria® 10 GX FPGA can access this flash device. The MAX® V CPLD accesses is for the FPP configuration of the FPGA at power-on and board reset events. This uses the Altera Parallel Flash Loader (PFL) IP. The Arria® 10 GX FPGA access to the FLASH’s user space will be done by Nios® II for the Board Update Portal (BUP) application. The flash is wired for the WORD mode operation to support FPP×32 download directly.

The table below shows the memory map for the onboard flash. This memory provides non-volatile storage for two FPGA bit-streams as well as various settings for data used for the BUP image and onboard devices such as PFL configuration bits.
Table 21.  Flash Memory Map
Block Description Size (KB) Address
Board Test System 512 0x09F4.0000 – 09FB.FFFF
User Software 14,336 0x0914.0000 – 09F3.FFFF
Factory Software 8,192 0x0894.0000 – 0913.FFFF
zipfs 8,192 0x0814.0000 – 0893.FFFF
User Hardware 2 44,032 0x0564.0000 – 0813.FFFF
User Hardware 1 44,032 0x02B4.0000 – 0563.FFFF
Factory Hardware 44,032 0x0004.0000 – 02B3.FFFF
PFL Option Bits 64 0x0003.0000 – 0003.FFFF
Board Information 64 0x0002.0000 – 0002.FFFF
Ethernet Option Bits 64 0x0001.0000 – 0001.FFFF
User Design Reset 64 0x0000.0000 – 0000.FFFF

Each FPGA bit stream can be a maximum of 254.25 Mbits (or less than 32 MBytes) for the Arria® 10 GX FPGA device. The remaining area is designated as RESERVED flash area for storage of the BUP image and PFL configuration settings, software binaries, and other data relevant to the FPGA design.

Table 22.  Flash Memory Pin Assignments, Signal Names and FunctionsThis table lists the flash pin assignments, signal names and functions
FLASH Memory Device Pin Number (U33/ U34) Schematic Signal Name Description Arria® 10 GX Device Pin Number
A1 (U33/U34) FM_A1 Address Bus F28
B1 (U33/U34) FM_A2 Address Bus F27
C1 (U33/U34) FM_A3 Address Bus G28
D1 (U33/U34) FM_A4 Address Bus G27
D2 (U33/U34) FM_A5 Address Bus H25
A2 (U33/U34) FM_A6 Address Bus G25
C2 (U33/U34) FM_A7 Address Bus K27
A3 (U33/U34) FM_A8 Address Bus D31
B3 (U33/U34) FM_A9 Address Bus C31
C3 (U33/U34) FM_A10 Address Bus C30
D3 (U33/U34) FM_A11 Address Bus C29
C4 (U33/U34) FM_A12 Address Bus E30
A5 (U33/U34) FM_A13 Address Bus E31
B5 (U33/U34) FM_A14 Address Bus E29
C5 (U33/U34) FM_A15 Address Bus D29
D7 (U33/U34) FM_A16 Address Bus F30
D8 (U33/U34) FM_A17 Address Bus F29
A7 (U33/U34) FM_A18 Address Bus J29
B7 (U33/U34) FM_A19 Address Bus K31
C7 (U33/U34) FM_A20 Address Bus K30
C8 (U33/U34) FM_A21 Address Bus L30
A8 (U33/U34) FM_A22 Address Bus L29
G1 (U33/U34) FM_A23 Address Bus G30
H8 (U33/U34) FM_A24 Address Bus G31
B6 (U33/U34) FM_A25 Address Bus H29
B8 (U33/U34) FM_A26 Address Bus H30
F2 (U33) FM_D0 Data Bus H34
E2 (U33) FM_D1 Data Bus J33
G3 (U33) FM_D2 Data Bus J32
E4 (U33) FM_D3 Data Bus L34
E5 (U33) FM_D4 Data Bus K34
G5 (U33) FM_D5 Data Bus N34
G6 (U33) FM_D6 Data Bus M35
H7 (U33) FM_D7 Data Bus M32
E1 (U33) FM_D8 Data Bus L32
E3 (U33) FM_D9 Data Bus U32
F3 (U33) FM_D10 Data Bus T32
F4 (U33) FM_D11 Data Bus R30
F5 (U33) FM_D12 Data Bus R31
H5 (U33) FM_D13 Data Bus U33
G7 (U33) FM_D14 Data Bus T33
E7 (U33) FM_D15 Data Bus N33
F2 (U34) FM_D16 Data Bus P33
E2 (U34) FM_D17 Data Bus R34
G3 (U34) FM_D18 Data Bus P34
E4 (U34) FM_D19 Data Bus T34
E5 (U34) FM_D20 Data Bus T35
G5 (U34) FM_D21 Data Bus D26
G6 (U34) FM_D22 Data Bus E26
H7 (U34) FM_D23 Data Bus A28
E1 (U34) FM_D24 Data Bus A27
E3 (U34) FM_D25 Data Bus B28
F3 (U34) FM_D26 Data Bus B27
F4 (U34) FM_D27 Data Bus B26
F5 (U34) FM_D28 Data Bus C26
H5 (U34) FM_D29 Data Bus D27
G7 (U34) FM_D30 Data Bus E27
E7 (U34) FM_D31 Data Bus C28
E6 (U33/U34) FLASH_CLK Clock AU31
D4 (U33/U34) FLASH_RESETn Reset AP31
B4 (U33) FLASH_CEn0 Chip Enable 0 AT30
B4 (U34) FLASH_CEn1 Chip Enable 1 AR31
F8 (U33/U34) FLASH_OEn Output Enable AT34
G8 (U33/U34) FLASH_WEn Write Enable AR35
F6 (U33/U34) FLASH_ADVn Address Valid AU30
C6 (U33/U34) FLASH_WPn Write Protect ----
F7 (U33) FLASH_RDYBSYn0 Ready / Busy AT35
F7 (U34) FLASH_RDYBSYn1 Ready / Busy AN31
- When using a single ×16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software. When using dual ×16 flash devices for an equivalent ×32 (×16||×16) flash device a word consists of 32 data bits so addressing starts with FM_A1 mapped to address bit 2 in software.
Level Two Title