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A.1. CFI Flash Memory Map
A.2. Preparing Design Files for Flash Programming
A.3. Creating Flash Files Using the Nios II EDS
A.4. Programming Flash Memory Using the Board Update Portal
A.5. Programming Flash Memory Using the Nios II EDS
A.6. Restoring the Flash Device to the Factory Settings
A.7. Restoring the MAX V CPLD to the Factory Settings
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6.4.2.2. MAX V Registers
The MAX V registers control allows you to view and change the current MAX V register values as described in the table below. Changes to the register values with the GUI take effect immediately.
MAX V Register Values | Description |
---|---|
SRST | Resets the system and reloads the FPGA with a design from flash memory based on the other MAX V register values. |
PSO | Sets the MAX V PSO register. |
PSR | Sets the MAX V PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA reconfiguration. |
PSS | Displays the MAX V PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration. |
Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running.