Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Public
Document Table of Contents

5.4.1. FPGA Programming over Embedded USB-Blaster

The figure below shows the high-level conceptual block diagram for the embedded USB-Blaster.
Figure 4. USB-Blaster Conceptual Block Diagram
The figure below shows a more detailed schematic block diagram for the embedded USB-Blaster interfacing to the Intel® Arria® 10 GX FPGA device.
Figure 5. Detailed USB-Blaster to FPGA Schematic

The embedded USB Blaster core for USB-based configuration of the Intel® Arria® 10 GX FPGA device is implemented using a TYPE B USB connector, a CY7C68013A USB2 PHY device, and an Altera MAX II EPM570M100 CPLD. This will allow configuration of the Intel® Arria® 10 GX FPGA device using a USB cable directly connected to a PC running Intel® Quartus® Prime software without requiring the external USB Blaster dongle. This design will convert USB data to interface with the Intel® Arria® 10 GX FPGA’s dedicated JTAG port. An LED (D4) is provided to indicate USB Blaster activity. The embedded USB blaster is automatically disabled when an external USB Blaster dongle is connected to the JTAG chain.