Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Public
Document Table of Contents

5.4.2. FPGA Programming from Flash Memory

The figure below shows the high-level conceptual block diagram for the MAX® V + Flash Fast Passive Parallel (FPP) configuration.
Figure 6. MAX V + Flash FPP x32 Configuration Conceptual Diagram
The figure below shows a more detailed schematic block diagram for the MAX® V + Flash FPP mode implementation.
Figure 7. Detailed MAX V + Flash FPP x32 Configuration Schematic

Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its Flash interface signals to avoid contention with the FPGA. A PGMSEL dipswitch (SW3) is provided to select between two POF files (FACTORY or USER) stored on the Flash. The Parallel Flash Loader (PFL) Megafunction will be used to implement FPP x32 configuration in the MAX® V CPLD. The PFL Megafunction reads data from the flash and converts it to Fast Passive Parallel format. This data is written to the Intel® Arria® 10 FPGA device dedicated DCLK and D[31:0] configuration pins at 50 MHz. The actual configuration data rate is limited by the flash read speed.

Implementation will be done using an Altera MAX® V 5M2210ZF256FBGA CPLD acting as the FPP download controller and two 1G Flash devices. The flash will be a Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX® V CPLD will share the CFI Flash interface with the Intel® Arria® 10 GX FPGA. No arbitration is needed between the MAX® V CPLD and Intel® Arria® 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization.

After a POWER-ON or RESET (re-configuration) event, the MAX® V device will configure the Arria 10 GX FPGA in FPP x32 mode with either the FACTORY POF or a USER defined POF depending on the FACTORY_LOAD setting. The PGMSEL bit is set via a pushbutton and observing the appropriate LED indicating a Factory or User file to be loaded. After selection of the program file; another pushbutton is press to load the program; that button is the PGM_CONFIG button.

The MSEL [2:0] pins indicate which passive mode is being used and whether the Fast or Slow POR delay is chosen. The data bus width information is contained in the Mode Select Decode Frame that is part of the configuration data. PORSEL is an internal signal decoded from MSEL[2:0] pins. PORSEL = 1 selects a Fast POR delay between 4-12ms. PORSEL = 0 selects a Slow POR delay between 100-300ms.The manufacturing default condition should be [000] for a Fast POR Delay mode without decompression or security enabled.

The 4 modes of Passive Programming are passive serial, passive parallel x8, passive parallel x16, and passive parallel x32.

For FPPx32 modes, MSEL [2:0] signals need to be set according to the table below
Table 7.  Supported FPPx32 Modes
MSEL[2:0] Mode of Operation Voltages Supported (v) POR Delay (ms)
000 Passive Fast 1.8 4-12
001 Passive Slow 1.8 100-300
010 Active Fast 1.8 4-12
011 Active Slow 1.8 100-300
100 ATPG 1.8 4-12
101 Test 1.8 4-12
110 Test Verify 1.8 4-12
111 Regscan 1.8 4-12
The LEDs associated with program load of FPPx32 mode configuration status as follows:
  • PGM_LED0 : ON when FACTORY image is selected
  • PGM_LED1 : ON when USER #1 image is selected
  • PGM_LED2 : ON when USER #2 image is selected
  • MAX_ERROR : ON when a Configuration Error has occurred
  • MAX_LOAD : ON when image is being loaded
  • MAX_CONF_DONE : ON when FPGA is successfully configured
Note: All the LEDs listed above are green.