Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 12/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide A. Programming the Flash Memory Device B. Safety and Regulatory Compliance Information
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Installing the Quartus® Prime Software 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria® 10 FPGA 5.3. MAX® V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria® 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External Intel® FPGA Download Cable
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded Intel® FPGA Download Cable Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitor 6.4.9. Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX® V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. XCVR1 Tab—Status 6.4.5.2. XCVR1 Tab—Port 6.4.5.3. XCVR1 Tab—PMA Setting 6.4.5.4. XCVR1 Tab—Data Type 6.4.5.5. XCVR1 Tab—Error Control 6.4.5.6. XCVR1 Tab—Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. XCVR2 Tab—Status 6.4.6.2. XCVR2 Tab—Port 6.4.6.3. XCVR2 Tab—PMA Setting 6.4.6.4. XCVR2 Tab—Data Type 6.4.6.5. XCVR2 Tab—Error Control 6.4.6.6. XCVR2 Tab—Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. XCVR3 Tab—Status 6.4.7.2. XCVR3 Tab—Port 6.4.7.3. XCVR3 Tab—PMA Setting 6.4.7.4. XCVR3 Tab—Data Type 6.4.7.5. XCVR3 Tab—Error Control 6.4.7.6. XCVR3 Tab—Run Control
6.4.9. Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX® V CPLD to the Factory Settings
B. Safety and Regulatory Compliance Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide
A. Programming the Flash Memory Device
B. Safety and Regulatory Compliance Information

5.1. Board Overview

This section provides an overview of the Arria® 10 GX transceiver signal integrity development board, including an annotated board image and component descriptions.
Figure 3. Overview of the Arria® 10 GX Transceiver Signal Integrity Development Board Features
Table 3.  Transceiver Signal Integrity Development Kit Components
Board Reference Type Description
Featured Devices
U51 FPGA Arria® 10 GX1150 FPGA (10AX115F1932C)
U32 CPLD MAX® V CPLD (5M2210ZF256), 256-pin BGA
General User Input and Output
D13–D20 User LEDs (Green) User LEDs (Green)
D21–D26 MAX® V LEDs (Green) MAX® V LEDs (Green)
S1–S12 User push buttons User push buttons
SW2, SW6 User DIP switches User DIP switches
SW3 MAX® V DIP Switch MAX® V DIP Switch
J20 LCD Display header Connector for 16 character × 2 line LCD I2C
Configuration, Status and Setup Elements
J66 Intel® FPGA Download Cable programming header (uses JTAG mode only) Header to interface external Intel® FPGA Download Cable direct to FPGA (through USB2 MAX2)
D4 Green LED USB2 Transmit-Receive Activity
D8–D12 Ethernet LEDs Ethernet LEDs (TX/RX/LINK)
Clock Circuitry
X3 25-MHz oscillator This 25-MHz oscillator is the clock source to clock buffer ICS557-03 that provides selectable frequencies and spread percentages of its differential outputs.
X4 50-MHz oscillator This 50-MHz oscillator is the clock source to clock buffer SL18860DC that provides three 50 MHz outputs to the FPGA (×2) and the MAX® V (×1)
SW4 Spread spectrum / frequency selection switch

SW4 selects frequency and spread spectrum percentages of clock buffer outputs ICS557-03. Refer to the SW-4 Board Reference table for additional details.
J49–J50 External core clock input SMA External input at CLKIN_3B0 p/n
J51–J52 External core clock output SMA external output at PLL_3B_CLKOUT0 p/n
Y3 Transceiver dedicated reference clock / programmable oscillator Feeds REFCLKs on left side of the Arria® 10 GX device and an LVDS trigger output at board reference J100/J101. The external input is available at board reference J53 and J54. The default frequency is 644.53125 MHz.
Y4 Transceiver dedicated reference clock / programmable oscillator Feeds REFCLKs on left side of the Arria® 10 GX device and an LVDS trigger output at board reference J102/J103. The external input is available at board reference J56 and J57. The default frequency is 706.25 MHz.
Y5 Transceiver dedicated reference clock / programmable oscillator Feeds REFCLKs on right side of the Arria® 10 GX device and an LVDS trigger output at board reference J104/J105. The external input is available at board reference J59 and J60. The default frequency is 625 MHz.
Y6 Transceiver dedicated reference clock / programmable oscillator Feeds REFCLKs on right side of the Arria® 10 GX device and an LVDS trigger an output at board reference J106/J107. The external input is available at board reference J62 and J63. The default frequency is 875 MHz.
Y2 Global clock / 25 MHz oscillator 25-MHz crystal oscillator input to Si5338A clock buffer that feeds core fabric
X5 Global clock / 125 MHz oscillator Feeds core fabric at CLKIN_2L0 p/n
Transceiver Interfaces
J46 High density connector 15 Gbps, 5 channels high density connector
J47 High density connector 15 Gbps, 5 channels high density connector

J30–J45

J67–J74

 2.4 mm SMA connector 25.78 Gbps, 4 channels 2.4 mm SMA connector
J24 CFP2 optical transceiver interface 25.78 Gbps, 4 transceiver channels connected to the CFP2 module
J23, J25, J26, J27 CFP2 optional MCLK input/output

CFP2 Tx MCLK SMA connectors

CFP2 Rx MCLK SMA connectors
J28 QSFP+ optical transceiver interface 25.78 Gbps, 4 transceiver channels connected to the QSFP+ module
J29 SFP+ optical transceiver interface 14 Gbps, single transceiver channel connected to the SFP+ module.
J22 Backplane connector 17 Gbps, 4 transceiver channels connected to the Amphenol backplane connector
Memory Devices
U33, U34 Flash memory Two 1-Gbit Micron PC28F00AP30BF CFI flash device
Communication Ports
J19 Gigabit Ethernet port RJ-45 connector which provides a 10/100/1000 Ethernet connection through a Marvell 88E1111 PHY
CN1 USB Type-B connector Connects a type-B USB cable
Power Supply
U209 LTM 2987 Linear Technology Power monitor device
U225 LTC2974 Linear Technology Power monitor device
Table 4.  SW-4 Board Reference
Board Reference Spread Spectrum/ Frequency Selection Switch Spread Spectrum Buffer Inputs  
SW4-1 S0
S1 S0 CLK Freq (MHz)
0 0 25
0 1 100
1 0 125
1 1 200
SW4-2 S1
SW4-3 SS0
SS1 SS0 Spread %
0 0 ±25
0 1 -0.5
1 0 -0.75
1 1 no spread
SW4-4 SS1
Level Two Title