Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 12/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide A. Programming the Flash Memory Device B. Safety and Regulatory Compliance Information
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Installing the Quartus® Prime Software 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria® 10 FPGA 5.3. MAX® V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria® 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External Intel® FPGA Download Cable
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded Intel® FPGA Download Cable Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitor 6.4.9. Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX® V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. XCVR1 Tab—Status 6.4.5.2. XCVR1 Tab—Port 6.4.5.3. XCVR1 Tab—PMA Setting 6.4.5.4. XCVR1 Tab—Data Type 6.4.5.5. XCVR1 Tab—Error Control 6.4.5.6. XCVR1 Tab—Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. XCVR2 Tab—Status 6.4.6.2. XCVR2 Tab—Port 6.4.6.3. XCVR2 Tab—PMA Setting 6.4.6.4. XCVR2 Tab—Data Type 6.4.6.5. XCVR2 Tab—Error Control 6.4.6.6. XCVR2 Tab—Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. XCVR3 Tab—Status 6.4.7.2. XCVR3 Tab—Port 6.4.7.3. XCVR3 Tab—PMA Setting 6.4.7.4. XCVR3 Tab—Data Type 6.4.7.5. XCVR3 Tab—Error Control 6.4.7.6. XCVR3 Tab—Run Control
6.4.9. Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX® V CPLD to the Factory Settings
B. Safety and Regulatory Compliance Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Document Revision History for the Arria® 10 GX Transceiver Signal Integrity Development Kit User Guide
A. Programming the Flash Memory Device
B. Safety and Regulatory Compliance Information

5.3. MAX® V CPLD

The Arria® 10 GX Transceiver Signal Integrity Development Kit consists of a MAX® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX® V CPLD devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring, FPGA configuration, and analog IC interface. MAX® V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX® V CPLDs can help you meet your low power design requirement.

The following list summarizes the MAX® V device features:
  • 2210 Logic Elements (LEs)
  • 8192 bits of User Flash Memory
  • 4 global clocks
  • 1 internal oscillator
  • 271 maximum user I/O pins
  • Low-cost, low power and non-volatile CPLD architecture
  • Fast propagation delays and clock-to-output times
  • Single 1.8 V external supply for device core
  • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
The table below lists the MAX® V CPLD Pin-out, the I/O signals present on the MAX® V CPLD.
Table 6.   MAX® V CPLD Device Pin-Out
Schematic Signal Name MAX® V CPLD Pin Number Arria® 10 GX Pin Number Description
FPGA_CONFIG_D0 D3 AU27 FPP configuration data bus
FPGA_CONFIG_D1 C2 AU28 FPP configuration data bus
FPGA_CONFIG_D2 C3 AP28 FPP configuration data bus
FPGA_CONFIG_D3 E3 AR29 FPP configuration data bus
FPGA_CONFIG_D4 D2 AT28 FPP configuration data bus
FPGA_CONFIG_D5 E4 AT29 FPP configuration data bus
FPGA_CONFIG_D6 D1 AW27 FPP configuration data bus
FPGA_CONFIG_D7 E5 AY27 FPP configuration data bus
FPGA_CONFIG_D8 F3 AY26 FPP configuration data bus
FPGA_CONFIG_D9 E1 AW26 FPP configuration data bus
FPGA_CONFIG_D10 F4 AV26 FPP configuration data bus
FPGA_CONFIG_D11 F2 AU26 FPP configuration data bus
FPGA_CONFIG_D12 F1 AV29 FPP configuration data bus
FPGA_CONFIG_D13 F6 AV30 FPP configuration data bus
FPGA_CONFIG_D14 G2 AV31 FPP configuration data bus
FPGA_CONFIG_D15 G3 AW31 FPP configuration data bus
FPGA_CONFIG_D16 G1 AW28 FPP configuration data bus
FPGA_CONFIG_D17 G4 AV28 FPP configuration data bus
FPGA_CONFIG_D18 H2 AY31 FPP configuration data bus
FPGA_CONFIG_D19 G5 AY30 FPP configuration data bus
FPGA_CONFIG_D20 H3 BA29 FPP configuration data bus
FPGA_CONFIG_D21 J1 BA30 FPP configuration data bus
FPGA_CONFIG_D22 J2 BA32 FPP configuration data bus
FPGA_CONFIG_D23 H4 BB32 FPP configuration data bus
FPGA_CONFIG_D24 K2 BA33 FPP configuration data bus
FPGA_CONFIG_D25 K5 BB33 FPP configuration data bus
FPGA_CONFIG_D26 L1 BB31 FPP configuration data bus
FPGA_CONFIG_D27 L2 BC31 FPP configuration data bus
FPGA_CONFIG_D28 K3 BC33 FPP configuration data bus
FPGA_CONFIG_D29 M2 BD33 FPP configuration data bus
FPGA_CONFIG_D30 L4 BA34 FPP configuration data bus
FPGA_CONFIG_D31 L3 BB35 FPP configuration data bus
FM_A1 C14 F28 Flash address bus
FM_A2 C15 F27 Flash address bus
FM_A3 E13 G28 Flash address bus
FM_A4 E12 G27 Flash address bus
FM_A5 D15 H25 Flash address bus
FM_A6 F14 G25 Flash address bus
FM_A7 D16 K27 Flash address bus
FM_A8 F13 D31 Flash address bus
FM_A9 E15 C31 Flash address bus
FM_A10 E16 C30 Flash address bus
FM_A11 F15 C29 Flash address bus
FM_A12 G14 E30 Flash address bus
FM_A13 F16 E31 Flash address bus
FM_A14 G13 E29 Flash address bus
FM_A15 G15 D29 Flash address bus
FM_A16 G12 F30 Flash address bus
FM_A17 G16 F29 Flash address bus
FM_A18 H14 J29 Flash address bus
FM_A19 H15 K31 Flash address bus
FM_A20 H13 K30 Flash address bus
FM_A21 H16 L30 Flash address bus
FM_A22 J13 L29 Flash address bus
FM_A23 R3 G30 Flash address bus
FM_A24 P5 G31 Flash address bus
FM_A25 T2 H29 Flash address bus
FM_A26 P9 H30 Flash address bus
FM_D0 J14 H34 Flash data bus
FM_D1 J15 J33 Flash data bus
FM_D2 K16 J32 Flash data bus
FM_D3 K13 L34 Flash data bus
FM_D4 K15 K34 Flash data bus
FM_D5 K14 N34 Flash data bus
FM_D6 L16 M35 Flash data bus
FM_D7 L11 M32 Flash data bus
FM_D8 L15 L32 Flash data bus
FM_D9 L12 U32 Flash data bus
FM_D10 M16 T32 Flash data bus
FM_D11 L13 R30 Flash data bus
FM_D12 M15 R31 Flash data bus
FM_D13 L14 U33 Flash data bus
FM_D14 N16 T33 Flash data bus
FM_D15 M13 N33 Flash data bus
FM_D16 N15 P33 Flash data bus
FM_D17 N14 R34 Flash data bus
FM_D18 P15 P34 Flash data bus
FM_D19 P14 T34 Flash data bus
FM_D20 D13 T35 Flash data bus
FM_D21 D14 D26 Flash data bus
FM_D22 F11 E26 Flash data bus
FM_D23 J16 A28 Flash data bus
FM_D24 F12 A27 Flash data bus
FM_D25 K12 B28 Flash data bus
FM_D26 M14 B27 Flash data bus
FM_D27 N13 B26 Flash data bus
FM_D28 R1 C26 Flash data bus
FM_D29 P4 D27 Flash data bus
FM_D30 N5 E27 Flash data bus
FM_D31 P6 C28 Flash data bus
USB_MAX5_CLK H5 — USB clock
CLK_CONFIG J5 — 100 MHz clock
50MHz_MAX5_CLK J12 — Dedicated 50 MHz MAX® V clock input
FPGA_nSTATUS J4 AN29 FPGA status
FPGA_CONF_DONE K1 AP27 FPGA configuration complete
FPGA_DCLK J3 AM26 FPGA configuration clock
FPGA_PR_ERROR P2 BA28 FPGA configuration error
FPGA_PR_READY E2 BB30 FPGA configuration ready
FPGA_PR_REQUEST F5 BD31 FPGA configuration request
FPGA_PR_DONE H1 BB28 FPGA configuration complete
FPGA_INIT_DONE K4 BC29 FPGA initialization complete
M5_JTAG_TCK P3 — JTAG chain Test clock input
M5_JTAG_TDI L6 — JTAG chain test data input
M5_JTAG_TDO M5 — JTAG chain test data output
M5_JTAG_TMS N4 — JTAG chain test mode select
TEMP_ALERTn D4 — Temperature alert
OVERTEMPn B1 — Over-temperature indicator LED
OVERTEMP C5 — Over-temperature status bit
MAX_CONF_DONE E11 — MAX® V configuration done
PGM_SEL B13 — Flash memory PGM select
PGM_CONFIG D12 — Flash memory PGM Configuration
PGM_LED0 B14 — Flash memory PGM select indicator 0
PGM_LED1 C13 — Flash memory PGM select indicator 1
PGM_LED2 B16 — Flash memory PGM select indicator 2
CLK_SEL A13 — Clock select (DIP switch set)
CLK_ENABLE A15 — Clock enable (DIP switch set)
FACTORY_LOAD A2 — Factory image for configuration
MAX_ERROR A4 — MAX® V error indicator LED
MAX_LOAD A6 — MAX® V load indicator LED
MSEL0 B10 AN26 DIP - FPGA mode select 0
MSEL1 B3 AL28 DIP - FPGA mode select 1
MSEL2 C10 AK25 DIP - FPGA mode select 2
CPU_RESETn C12   CPU reset (via push button)
I2C_18V_SCL C7 AM35 I2C clock, 1.8 V leg of I2C Chain
I2C_18V_SDA D10 AK32 I2C data, 1.8 V leg of I2C Chain
CLK_125MHz_EN D5 — 125 MHz clock enable
CLK_50MHz_EN E8 — 50 MHz clock enable
FLASH_WEn N6 AR35 Flash write enable
FLASH_CEn0 R5 AT30 Flash chip enable
FLASH_CEn1 M7 AR31 Flash chip enable
FLASH_OEn M6 AT34 Flash output enable
FLASH_RDYBSYn0 T5 AT35 Flash chip ready/busy
FLASH_RDYBSYn1 R7 AN31 Flash chip ready/busy
FLASH_RESETn P7 AP31 Flash Reset
FLASH_CLK R6 AU31 Flash clock
FLASH_ADVn N7 AU30 Flash address valid
MAX_RESETn M9 — MAX® V reset
MAX5_SWITCH R12 — MAX® V switch (via DIP switch)
MAX5_OEn M10 AG32 MAX® V output enable
MAX5_CSn R10 W32 MAX® V chip select
MAX5_WEn N10 W33 MAX® V write enable
MAX5_CLK T11 AA34 MAX® V clock
MAX5_BEn0 P10 W35 MAX® V byte enable 0
MAX5_BEn1 R11 Y35 MAX® V byte enable 1
MAX5_BEn2 T12 V33 MAX® V byte enable 2
MAX5_BEn3 N11 V34 MAX® V byte enable 3
ENET_INTn R16 AW12 Ethernet interrupt
ENET_RSTn P13 AV13 Ethernet reset
FAN_RPM N9 — Fan RPM control
USB_CFG0 R4 — USB configuration bits
USB_CFG1 T4 — USB configuration bits
USB_CFG2 P8 — USB configuration bits
USB_CFG3 T7 — USB configuration bits
USB_CFG4 N8 — USB configuration bits
USB_CFG5 R8 — USB configuration bits
USB_CFG6 T8 — USB configuration bits
USB_CFG7 T9 — USB configuration bits
USB_CFG8 R9 — USB configuration bits
Level Two Title