Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Document Table of Contents

3.1. Setting Up the Board

To prepare and apply power to the board, perform the following steps:

  1. The Intel® Arria® 10 GX transceiver signal integrity development kit ships with its board switches pre-configured to support the design examples in the kit. If you suspect your board might not be currently configured with the default settings, follow the instructions in Factory Default Switch Settings to return the board to its factory settings before proceeding.
  2. The development kit ships with design examples stored in the flash memory device. A slide switch is provided to turn the board power ON or OFF. When the switch SW1 is powered on, two green LEDs will illuminate to indicate that all power is applied to the board. These two LEDs are driven by the power circuitry when the power switch is turned ON. RESET button is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for FPP configuration.
    When the power cord is plugged into connector J1 of the Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit, 12V and 5V are present on the board with switch SW1 in the ‘OFF’ position. These voltages are restricted to a small area of the board. When switch SW1 is placed to ‘ON’ position, all voltage planes have power at this point.
  3. When this button is pressed, the MAX® V CPLD will initiate a reloading of the stored image from flash memory using FPP configuration mode. The image loaded right after power cycle or MAX® V reset depends on FACTORY_LOAD settings: (1) OFF (1) - factory load (2) ON (0) user defined load #1. Page selection can be changed by PGMSEL button when the board is powered on, and PGM_CONFIG is used to reconfigure FPGA with corresponding page which is indicated by PGM_LED0, PGM_LED1 or PGM_LED2
    Use only the supplied power supply. Power regulation circuitry on the board can be damaged by power supplies with greater voltage.
  4. Set the POWER-ON switch SW1 to the on position. When power is supplied to the board, two green LEDs (D32 and D34) illuminates indicating that the board has power.

The MAX® V CPLD device on the board contains a parallel flash loader (PFL) megafunction. After a POWER-ON or RESET (reconfiguration) event, the MAX® V CPLD will configure the Arria 10 GX FPGA in FPP mode with either the FACTORY POF or a USER defined POF depending on the setting of FACTORY_LOAD. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this button and observing the program LEDs dictates which program will be selected. Then the PGM_CONFIG pushbutton needs to be pressed to load the program.

The kit includes a MAX® V CPLD design which contains the PFL megafunction. The design resides in the <package dir>\examples\max5 directory.
  1. When configuration is complete, LED D26 (CFGDN) illuminates signaling that the Intel® Arria® 10 GX FPGA device configured successfully.
  2. If the configuration fails, the LED 24 (ERROR) illuminates.