Arria 10 GX Transceiver Signal Integrity Development Kit User Guide
ID
683553
Date
8/08/2017
Public
A.1. CFI Flash Memory Map
A.2. Preparing Design Files for Flash Programming
A.3. Creating Flash Files Using the Nios II EDS
A.4. Programming Flash Memory Using the Board Update Portal
A.5. Programming Flash Memory Using the Nios II EDS
A.6. Restoring the Flash Device to the Factory Settings
A.7. Restoring the MAX V CPLD to the Factory Settings
5.8.2. User-Defined DIP Switch
Board reference SW2 and SW6 are two 4-pin DIP switches. The switches are user-defined, and are provides additional FPGA input control. When the switch is in the OPEN position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected. There is no board-specific function for these switches.
The table below lists the schematic signal names of each DIP switch and their corresponding Intel® Arria® 10 GX FPGA pin numbers.
Board Reference | Schematic Signal Name | Arria 10 GX Device Pin Number |
---|---|---|
SW6-1-8 | USER_DIP3 | BA18 |
SW6-2-7 | USER_DIP2 | BA17 |
SW6-3-6 | USER_DIP1 | BA20 |
SW6-4-5 | USER_DIP0 | BA19 |
SW2-4-5 | USER_DIP4 | BC21 |
SW2-3-6 | USER_DIP5 | BB21 |
SW2-2-7 | USER_DIP6 | BC20 |
SW2-1-8 | A10_UNLOCK | BB20 |