Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683553
Date 8/08/2017
Document Table of Contents


The Intel® Arria® 10 transceiver development kit consists of a MAX® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX® V CPLD devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring, FPGA configuration, and analog IC interface. MAX® V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX® V CPLDs can help you meet your low power design requirement.

The following list summarizes the MAX® V device features:
  • 2210 Logic Elements (LEs)
  • 8192 bits of User Flash Memory
  • 4 global clocks
  • 1 internal oscillator
  • 271 maximum user I/O pins
  • Low-cost, low power and non-volatile CPLD architecture
  • Fast propagation delays and clock-to-output times
  • Single 1.8V external supply for device core
  • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
The table below lists the MAX V CPLD Pin-out, the I/O signals present on the MAX V CPLD.
Table 6.  MAX V CPLD Device Pin-Out
Schematic Signal Name MAX V CPLD Pin Number Arria 10 GX Pin Number Description
FPGA_CONFIG_D0 D3 AU27 FPP Configuration Data Bus
FPGA_CONFIG_D1 C2 AU28 FPP Configuration Data Bus
FPGA_CONFIG_D2 C3 AP28 FPP Configuration Data Bus
FPGA_CONFIG_D3 E3 AR29 FPP Configuration Data Bus
FPGA_CONFIG_D4 D2 AT28 FPP Configuration Data Bus
FPGA_CONFIG_D5 E4 AT29 FPP Configuration Data Bus
FPGA_CONFIG_D6 D1 AW27 FPP Configuration Data Bus
FPGA_CONFIG_D7 E5 AY27 FPP Configuration Data Bus
FPGA_CONFIG_D8 F3 AY26 FPP Configuration Data Bus
FPGA_CONFIG_D9 E1 AW26 FPP Configuration Data Bus
FPGA_CONFIG_D10 F4 AV26 FPP Configuration Data Bus
FPGA_CONFIG_D11 F2 AU26 FPP Configuration Data Bus
FPGA_CONFIG_D12 F1 AV29 FPP Configuration Data Bus
FPGA_CONFIG_D13 F6 AV30 FPP Configuration Data Bus
FPGA_CONFIG_D14 G2 AV31 FPP Configuration Data Bus
FPGA_CONFIG_D15 G3 AW31 FPP Configuration Data Bus
FPGA_CONFIG_D16 G1 AW28 FPP Configuration Data Bus
FPGA_CONFIG_D17 G4 AV28 FPP Configuration Data Bus
FPGA_CONFIG_D18 H2 AY31 FPP Configuration Data Bus
FPGA_CONFIG_D19 G5 AY30 FPP Configuration Data Bus
FPGA_CONFIG_D20 H3 BA29 FPP Configuration Data Bus
FPGA_CONFIG_D21 J1 BA30 FPP Configuration Data Bus
FPGA_CONFIG_D22 J2 BA32 FPP Configuration Data Bus
FPGA_CONFIG_D23 H4 BB32 FPP Configuration Data Bus
FPGA_CONFIG_D24 K2 BA33 FPP Configuration Data Bus
FPGA_CONFIG_D25 K5 BB33 FPP Configuration Data Bus
FPGA_CONFIG_D26 L1 BB31 FPP Configuration Data Bus
FPGA_CONFIG_D27 L2 BC31 FPP Configuration Data Bus
FPGA_CONFIG_D28 K3 BC33 FPP Configuration Data Bus
FPGA_CONFIG_D29 M2 BD33 FPP Configuration Data Bus
FPGA_CONFIG_D30 L4 BA34 FPP Configuration Data Bus
FPGA_CONFIG_D31 L3 BB35 FPP Configuration Data Bus
FM_A1 C14 F28 Flash address bus
FM_A2 C15 F27 Flash address bus
FM_A3 E13 G28 Flash address bus
FM_A4 E12 G27 Flash address bus
FM_A5 D15 H25 Flash address bus
FM_A6 F14 G25 Flash address bus
FM_A7 D16 K27 Flash address bus
FM_A8 F13 D31 Flash address bus
FM_A9 E15 C31 Flash address bus
FM_A10 E16 C30 Flash address bus
FM_A11 F15 C29 Flash address bus
FM_A12 G14 E30 Flash address bus
FM_A13 F16 E31 Flash address bus
FM_A14 G13 E29 Flash address bus
FM_A15 G15 D29 Flash address bus
FM_A16 G12 F30 Flash address bus
FM_A17 G16 F29 Flash address bus
FM_A18 H14 J29 Flash address bus
FM_A19 H15 K31 Flash address bus
FM_A20 H13 K30 Flash address bus
FM_A21 H16 L30 Flash address bus
FM_A22 J13 L29 Flash address bus
FM_A23 R3 G30 Flash address bus
FM_A24 P5 G31 Flash address bus
FM_A25 T2 H29 Flash address bus
FM_A26 P9 H30 Flash address bus
FM_D0 J14 H34 Flash data bus
FM_D1 J15 J33 Flash data bus
FM_D2 K16 J32 Flash data bus
FM_D3 K13 L34 Flash data bus
FM_D4 K15 K34 Flash data bus
FM_D5 K14 N34 Flash data bus
FM_D6 L16 M35 Flash data bus
FM_D7 L11 M32 Flash data bus
FM_D8 L15 L32 Flash data bus
FM_D9 L12 U32 Flash data bus
FM_D10 M16 T32 Flash data bus
FM_D11 L13 R30 Flash data bus
FM_D12 M15 R31 Flash data bus
FM_D13 L14 U33 Flash data bus
FM_D14 N16 T33 Flash data bus
FM_D15 M13 N33 Flash data bus
FM_D16 N15 P33 Flash data bus
FM_D17 N14 R34 Flash data bus
FM_D18 P15 P34 Flash data bus
FM_D19 P14 T34 Flash data bus
FM_D20 D13 T35 Flash data bus
FM_D21 D14 D26 Flash data bus
FM_D22 F11 E26 Flash data bus
FM_D23 J16 A28 Flash data bus
FM_D24 F12 A27 Flash data bus
FM_D25 K12 B28 Flash data bus
FM_D26 M14 B27 Flash data bus
FM_D27 N13 B26 Flash data bus
FM_D28 R1 C26 Flash data bus
FM_D29 P4 D27 Flash data bus
FM_D30 N5 E27 Flash data bus
FM_D31 P6 C28 Flash data bus
USB_MAX5_CLK H5 ---- USB Clock
CLK_CONFIG J5 ---- 100 MHz Clock
50MHz_MAX5_CLK J12 ---- Dedicated 50 MHz MAX V clock input
FPGA_CONF_DONE K1 AP27 FPGA Configuration complete
FPGA_DCLK J3 AM26 FPGA configuration clock
FPGA_PR_ERROR P2 BA28 FPGA configuration error
FPGA_PR_READY E2 BB30 FPGA configuration ready
FPGA_PR_REQUEST F5 BD31 FPGA configuration request
FPGA_PR_DONE H1 BB28 FPGA configuration complete
FPGA_INIT_DONE K4 BC29 FPGA initialization complete
M5_JTAG_TCK P3 ---- JTAG chain Test clock input
M5_JTAG_TDI L6 ---- JTAG chain test data input
M5_JTAG_TDO M5 ---- JTAG chain test data output
M5_JTAG_TMS N4 ---- JTAG chain test mode select
TEMP_ALERTn D4 ---- Temperature Alert
OVERTEMPn B1 ---- Over-temperature indicator LED
OVERTEMP C5 ---- Over-temperature status bit
MAX_CONF_DONE E11 ---- MAX V Configuration Done
PGM_SEL B13 ---- Flash memory PGM select
PGM_CONFIG D12 ---- Flash memory PGM Configuration
PGM_LED0 B14 ---- Flash memory PGM select indicator 0
PGM_LED1 C13 ---- Flash memory PGM select indicator 1
PGM_LED2 B16 ---- Flash memory PGM select indicator 2
CLK_SEL A13 ---- Clock Select (dipswitch set)
CLK_ENABLE A15 ---- Clock Enable (dipswitch set)
FACTORY_LOAD A2 ---- Factory Image for Configuration
MAX_ERROR A4 ---- MAX V Error Indicator LED
MAX_LOAD A6 ---- MAX V Load Indicator LED
MSEL0 B10 AN26 DIP - FPGA mode select 0
MSEL1 B3 AL28 DIP - FPGA mode select 1
MSEL2 C10 AK25 DIP - FPGA mode select 2
CPU_RESETn C12   CPU Reset (via pushbutton)
I2C_18V_SCL C7 AM35 I2C Clock, 1.8V leg of I2C Chain
I2C_18V_SDA D10 AK32 I2C Data, 1.8V leg of I2C Chain
CLK_125MHz_EN D5 ---- 125 MHz Clock enable
CLK_50MHz_EN E8 ---- 50 MHz Clock Enable
FLASH_WEn N6 AR35 Flash write enable
FLASH_CEn0 R5 AT30 Flash chip enable
FLASH_CEn1 M7 AR31 Flash chip enable
FLASH_OEn M6 AT34 Flash output enable
FLASH_RDYBSYn0 T5 AT35 Flash chip ready/busy
FLASH_RDYBSYn1 R7 AN31 Flash chip ready/busy
FLASH_RESETn P7 AP31 Flash Reset
FLASH_CLK R6 AU31 Flash clock
FLASH_ADVn N7 AU30 Flash address valid
MAX_RESETn M9 ---- MAX V Reset
MAX5_SWITCH R12 ---- MAX V switch (via dipswitch)
MAX5_OEn M10 AG32 MAX V output enable
MAX5_CSn R10 W32 MAX V chip select
MAX5_WEn N10 W33 MAX V write enable
MAX5_CLK T11 AA34 MAX V clock
MAX5_BEn0 P10 W35 MAX V byte enable 0
MAX5_BEn1 R11 Y35 MAX V byte enable 1
MAX5_BEn2 T12 V33 MAX V byte enable 2
MAX5_BEn3 N11 V34 MAX V byte enable 3
ENET_INTn R16 AW12 Ethernet Interrupt
ENET_RSTn P13 AV13 Ethernet Reset
FAN_RPM N9 ---- Fan RPM Control
USB_CFG0 R4 ---- USB configuration bits
USB_CFG1 T4 ---- USB configuration bits
USB_CFG2 P8 ---- USB configuration bits
USB_CFG3 T7 ---- USB configuration bits
USB_CFG4 N8 ---- USB configuration bits
USB_CFG5 R8 ---- USB configuration bits
USB_CFG6 T8 ---- USB configuration bits
USB_CFG7 T9 ---- USB configuration bits
USB_CFG8 R9 ---- USB configuration bits