Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

BAS support is enabled on the hardware. Enable the following flag in user/common/include/ifc_libmqdma.h
#define PCIe_SLOT 0 /* 0 – x16, 1 – x8 */


To verify the write operation:
./cli/perfq_app/perfq_app -b 0000:01:00.0 -s 512 -e -t 
Figure 46. BAS Write Operation
To verify the read operation:
./cli/perfq_app/perfq_app -b 0000:01:00.0 -s 512 -e -r
Figure 47. BAS Read Operation
To verify the write and read operation:
./cli/perfq_app/perfq_app -b 0000:01:00.0 -s 512 -e -z
Figure 48. BAS Write and Read Operation

Performance test:

The below log is collected on Gen3x16 H-tile:
./cli/perfq_app/perfq_app -b 0000:01:00.0 -s 1048576 –-bas_perf -z
Figure 49. BAS Write and Read Performance Test

Did you find the information on this page useful?

Characters remaining:

Feedback Message