R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.4.1.1. Transmit Signals

Table 77.  PIPE Direct EMIB Data Channel Transmit SignalsIn the signal names, X is the lane number and ranges from 0 to 15.
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_txelecidle_i[3:0] Input One bit per two Symbols, for a maximum of 8 symbols. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid1_i Input This signal qualifies txdata[63:32]. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid0_i Input This signal qualifies txdata[31:0]. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdata_i[63:0] Input Transmit data bus pipe_direct_pld_tx_clk_out_o

The following timing diagrams provide an illustration of the behaviors of the PIPE Direct TX Datapath signals:

Figure 41. PIPE Direct TX Datapath
Note: At Gen1 and Gen2 speeds, only the 10 LSB bits from the lower segment of LnX_pipe_direct_txdata bus contain valid data. Bits [63:10] are don't-cares.

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