R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

2.3.2.2. Independent PERST

The R-Tile Avalon® Streaming IP for PCIe allows further flexibility to handle independent reset operation for each of the active PCIe cores. The active PCIe cores depend on the Configuration Mode selected for the IP. For more information on the Configuration Modes, refer to Configuration Modes Supported by the R-tile Avalon® Streaming IP for PCI Express.

When you enable the Enable Independent Perst parameter in the IP Parameter Editor, the additional pX_cold_perst_n_i, pX_warm_perst_n_i, and pX_ip_rst_n_o ports become available.

Consider the following guidelines for handling independent reset operations:
  • pin_perst_n or pX_cold_perst_n_i input ports can trigger a cold reset. This will clear sticky bits and reset the physical layer.
  • pX_warm_perst_n_i input ports can trigger a warm reset. This will not clear the sticky bits but will reset the physical layer.
    Input Port Used Sticky Bits Clearing Non-Sticky Bits Clearing PHY Lane Reset
    pin_perst_n Yes Yes Yes
    pX_cold_perst_n_i Yes Yes Yes
    pX_warm_perst_n_i No Yes Yes
  • pin_perst_n has the highest priority for reset over the pX_cold_perst_n_i or pX_warm_perst_n_i ports.
  • When pin_perst_n is asserted (i.e. low), all active PCIe cores will reset.

  • When pin_perst_n is deasserted (i.e. high), the pX_cold_perst_n_i input ports can be used to trigger a cold reset operation on each of the PCIe cores independently.

  • When pin_perst_n is deasserted (i.e. high), the pX_warm_perst_n_i input ports can be used to trigger a warm reset operation on each of the PCIe cores independently.
    Figure 6.  pX_cold_perst_n_i/pX_warm_perst_n_i vs. pin_perst_n Behavior
    Figure 7.  pX_cold_perst_n_i/pX_warm_perst_n_i Behavior
  • Concurrent assertions of the reset input ports pin_perst_n, pX_cold_perst_n_i and pX_warm_perst_n_i are not supported.
  • Usage of the pX_cold_perst_n_i to perform a cold reset to one of the active cores must happen only after the deassertion (i.e. high) of the corresponding pX_reset_status_n port. As an example, in Configuration Mode 2 (x8x8), in order to trigger an independent cold reset operation on p0_cold_perst_n_i, the p0_reset_status_n must be deasserted (i.e. high).
  • Usage of the pX_warm_perst_n_i to perform a warm reset to one of the active cores must happen only after the deassertion (i.e. high) of the corresponding pX_reset_status_n port. As an example, in Configuration Mode 2 (x8x8), in order to trigger an independent warm reset operation on p0_warm_perst_n_i, the p0_reset_status_n must be deasserted (i.e. high).
  • Similarly to the pin_perst_n, once pX_cold_perst_n_i has been asserted (i.e. low), the assertion needs to be held for a minimum of 100us.
  • Similarly to the pin_perst_n, once pX_warm_perst_n_i has been asserted (i.e. low), the assertion needs to be held for a minimum of 100us.
    Figure 8. Interval Between Subsequent Independent PERST Operations
  • pX_cold_perst_n_i or pX_warm_perst_n_i assertion should be avoided during a functional-level reset or before a functional-level reset is completed since this could impact the link training process. In case this occurs, assert pin_perst_n to properly complete the link training process.
  • When the pX_cold_perst_n_i or pX_warm_perst_n_i ports are routed to General Purpose I/Os (GPIOs), the Application logic must implement a debounce logic to prevent the switch bouncing and triggering unintentional assertions. The debounce logic consists of a counter that waits for the signal to stabilize before propagating it to the targeted port. In case these ports are not routed to GPIOs and are being used by internal fabric logic only, the debounce logic is not necessary.
    Figure 9.  pX_cold_perst_n_i/pX_warm_perst_n_i Signals Before and After Debounce Logic

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