R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

3.1. PCIe Port Bifurcation and PHY Channel Mapping

The PCIe* controller IP contains a set of port bifurcation muxes to remap the four controller PIPE lane interfaces to the shared 16 PCIe* PHY lanes. The table below shows the relationship between PHY lanes and the port mapping.

Table 12.  Port Bifurcation and PHY Channel Mapping
Bifurcation Mode Port 0 (x16) Port 1 (x8) Port 2 (x4) Port 3 (x4)
1 x16 0 - 15 NA NA NA
2 x8 0 - 7 8 - 15 NA NA
4 x4 4 - 7 8 - 11 0 - 3 12 - 15
Note: Port 2 is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.
Note: For more details on the bifurcation modes, refer to PCIe Hard IP Mode.

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