R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

3.3.4.1. Configuration TLP

The R-tile IP forwards any received Type0/1 Configuration TLP to the Avalon® -ST RX streaming interface. Application logic has the responsibility to respond with a Completion TLP with a Completion code of Successful Completion (SC), Unsupported Request (UR), Configuration Request Retry Status (CRS), or Completer Abort (CA).

If a Configuration TLP needs to update a register in the Lite PCIe configuration space in the R-tile PCIe Hard IP (shown in the figure below), you need to use the Hard IP Reconfiguration Interface.

The application logic needs to prevent link programming side effects such as writing into low-power states before sending the Completion associated with the request. The application logic can check the pX_tx_ehp_deallocate_empty_o signal after the Completion enters the TX streaming interface to confirm that the TLP has been sent. For more details on the Hard IP Reconfiguration Interface, refer to Hard IP Reconfiguration Interface.

Figure 21. Configuration TLP Received by R-tile IP for PCIe Targeting the Hard IP Internal Registers

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