6.3. Signal Tap Logic Analyzer
You can use the Signal Tap Logic Analyzer to monitor the top-level signals below from the R-tile Avalon-ST IP for PCIe as an additional debug tool for PCIe issues.
|Signal||Description||Expected Value for Successful Link-up|
A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. You need to instantiate the Reset Release IP and connect the output of that IP to ninit_done.
|pin_perst_n_o||This output signal to the FPGA fabric indicates if PERST# is asserted.||1'b1|
This active-low signal is held low until pin_perst_n has been deasserted and the PCIe Hard IP has come out of reset.
This signal is synchronous to coreclkout_hip. Traffic between the user logic in the FPGA core and the IP can start when pX_reset_status_n_o is asserted high.
|pX_link_up_o||When asserted, this signal indicates the link is up at the Physical Layer.||1'b1|
|pX_dl_up_o||When asserted, this signal indicates the Data link (DL) Layer is active.||1'b1|
|pX_ltssm_state_delay_o[5:0]||Indicates the LTSSM state. Note that there is a time difference between the actual link state at the physical level and the time it takes to reflect its value on this signal.||6'h11 (L0)|
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