R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.3.3.2. MSI

MSI interrupts are signaled on the PCI Express link using a single-dword Memory Write TLP. The user application issues an MSI request (MWr) through the Avalon® -ST interface and updates the configuration space register using the MSI interface.

Note: Only Ports 0 and 1 support MSI.
Table 61.  MSI Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_msi_pnd_func_i[2:0] Input Function number select for the Pending Bits register in the MSI capability structure. EP/BP slow_clk
pX_msi_pnd_addr_i[1:0] Input Byte select for the Pending Bits Register in the MSI Capability Structure. For example, if msi_pnd_addr_i[1:0] = 00, bits [7:0] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. If msi_pnd_addr_i[1:0] = 01, bits [15:8] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. EP/BP slow_clk
pX_msi_pnd_byte_i[7:0] Input Indicate that function has a pending associated message. EP slow_clk
pX_msi_pnd_ready_o Output

A value of 0 indicates the endpoint may be servicing another message, and unable to service this master immediately.

A new MSI event should be held until msi_pnd_ready_o = 1.

EP/BP slow_clk

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