R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.3.13. General Purpose VSEC Interface

Table 76.  General Purpose VSEC Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_pld_gp_ctrl_o[7:0] where

X = 0, 1, 2, 3 (IP core number)

Output General purpose VSEC control register value. EP/RP/BP slow_clk
pX_pld_gp_status_i[7:0] where

X = 0, 1, 2, 3 (IP core number)

Input General purpose VSEC status register value. EP/RP/BP slow_clk
pX_pld_gp_status_ready_o where

X = 0, 1, 2, 3 (IP core number)

Output

Value 0 indicates an input change is pending. The new value should be held if pX_pld_gp_status_ready_o = 0.

pX_pld_gp_status_ready_o = 1 when the interface is ready to accept the new value.

EP/RP/BP slow_clk

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