R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

3.2.2.4. VirtIO PCI Configuration Access Interface

To access a VirtIO device region, pci_cfg_data will provide a window of size cap.length (1, 2 or 4 Bytes) into the given cap.bar (0x0 – 0x5) at offset cap.offset (multiple of cap.length). Detailed interfaces mapping for the user application logic are shown in the following table.

As for the VirtIO device, upon detecting a driver write access to pci_cfg_data, the user application side's VirtIO device must execute a write access at cap.offset at the BAR selected by cap.bar using the first cap.length bytes from pci_cfg_data. Moreover, upon detecting a driver read access to pci_cfg_data, the user application side's VirtIO device must execute a read access of length cap.length at cap.offset at the BAR selected by cap.bar and store the first cap.length bytes in pci_cfg_data.

Table 16.  VirtIO PCI Configuration Access Interface
Name Direction Description Clock Domain
pX_virtio_pcicfg_vfaccess_o where X = 0, 1 O

Indicates the driver access is to a VF.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_vfnum_o.

slow_clk
pX_virtio_pcicfg_vfnum_o[VFNUM_WIDTH-1:0] where X = 0, 1 O

Indicates the corresponding Virtual Function number associated with the current Physical Function that the driver’s write or read access is targeting.

Validated by virtio_pcicfg_vfaccess_o and by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

slow_clk
pX_virtio_pcicfg_pfnum_o[PFNUM_WIDTH-1:0] where X = 0, 1 O

Indicates the corresponding Physical Function number that the driver’s write or read access is targeting.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

slow_clk
pX_virtio_pcicfg_bar_o[7:0] where X = 0, 1 O

Indicates the BAR holding the PCI configuration access structure. The driver sets the BAR to access by writing to cap.bar. Values 0x0 to 0x5 specify a BAR belonging to the function located beginning at 10h in the PCI Configuration Space. The BAR can be either 32-bit or 64-bit.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_length_o[31:0] where X = 0, 1 O

Indicates the length of the structure. The length may include padding, or fields unused by the driver, or future extensions. The driver sets the size of the access by writing 1, 2 or 4 to cap.length.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_baroffset_o[31:0] where X = 0, 1 O

Indicates where the structure begins relative to the base address associated with the BAR. The driver sets the offset within the BAR by writing to cap.offset.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_cfgdata_o[31:0] where X = 0, 1 O

Indicates the data for BAR access. The pci_cfg_data will provide a window of size cap.length into the given cap.bar at offset cap.offset.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_cfgwr_o where X = 0, 1 O

Indicates driver write access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_cfgrd_o where X = 0, 1 O

Indicates driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

slow_clk
pX_virtio_pcicfg_appvfnum_i[VFNUM_WIDTH-1:0] where X = 0, 1 I

Indicates the corresponding Virtual Function number associated with the current Physical Function that the application config data storage is for.

Validated by virtio_pcicfg_rdack_i.

slow_clk
pX_virtio_pcicfg_apppfnum_i[PFNUM_WIDTH-1:0] where X = 0, 1 I

Indicates the corresponding Physical Function number that the application config data storage is for.

Validated by virtio_pcicfg_rdack_i.

slow_clk
pX_virtio_pcicfg_rdack_i where X = 0, 1 I

Indicates an application read access data ack to store the config data in pci_cfg_data. Usually the reasonable ack latency is no more than 10 cycles.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

slow_clk
pX_virtio_pcicfg_rdbe_i[3:0] where X = 0, 1 I

Indicates application enabled bytes within virtio_pcicfg_data_i.

Validated by virtio_pcicfg_rdack_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

For the current implementation of the Hard IP, these signals are tied high.

slow_clk
pX_virtio_pcicfg_data_i[31:0] where X = 0, 1 I

Indicates application data to be stored in PCI Configuration Access data registers.

Validated by virtio_pcicfg_rdack_i and virtio_pcicfg_rdbe_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

slow_clk

Did you find the information on this page useful?

Characters remaining:

Feedback Message