R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

5.2.3. PCI Express and PCI Capabilities Parameters

For each core (PCIe0/PCIe1/PCIe2/PCIe3), the PCI Express / PCI Capabilities tab contains separate tabs for the device, link, device serial number (EP), power management, VSEC, PRS (EP), MSI (EP), MSI-X (EP), PASID (EP), ATS (EP), TPH, PTM (EP), VirtIO (EP), LTR (EP), ACS (RP), slot (RP), and legacy interrupt pin register (EP) parameters.

Note:
  • (EP) = the parameter is only available when the IP is in Endpoint mode.
  • (RP) = the parameter is only available when the IP is in Root Port mode.
  • Otherwise, the parameter is always available.
Figure 50. PCI Express and PCI Capabilities Parameters in Endpoint Mode
Figure 51. PCI Express and PCI Capabilities Parameters in Root Port Mode

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