R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

2.1. Overview

R-tile can be configured in one of three primary modes of operation:
  • PCIe Hard IP mode: This mode includes support for (up to Gen5) Endpoint (EP), Root Port (RP) or TLP Bypass (16 lanes maximum). When configured in this mode, R-tile includes a complete protocol stack, including the Transaction, Data Link and Physical Layers.
  • PIPE Direct (protocol controller bypass) for FPGA user custom application needs. In this mode, either one or both of the PCIe and CXL controller stacks are entirely bypassed, and the PIPE SerDes mode interface is exported across the Embedded Multi-die Interconnect Bridge (EMIB) to the FPGA fabric. This mode allows you to implement your own custom controllers in soft IP.
  • Compute Express Link (CXL).
Figure 1. R-tile Top-Level Block Diagram

Did you find the information on this page useful?

Characters remaining:

Feedback Message