R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2. Core Parameters

Depending on which Hard IP Mode you choose in the Top-Level Settings tab, you will see different tabs for setting the core parameters.

If you choose a 1x16 mode (Gen3, Gen4 or Gen5), only the PCIe0 Settings tab will appear.

Figure 47. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 1x16 Mode

If you choose a 2x8 mode (Gen3, Gen4 or Gen5), only the PCIe0 Settings and PCIe1 Settings tabs will appear.

Figure 48. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 2x8 Mode

If you choose a 4x4 mode (Gen3, Gen4 or Gen5), the PCIe0 Settings, PCIe1 Settings, PCIe2 Settings and PCIe3 Settings tabs will appear.

Figure 49. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 4x4 Mode