R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.3.10. Page Request Services (PRS) Interface (Endpoint Only)

When an Endpoint determines that it requires access to a page for which the ATS translation is not available, it sends a Page Request message to request that the page be mapped into system memory.

The PRS interface allows the monitoring of when PRS events happen, what functions these PRS events belong to, and what types of events they are.

The PRS interface is only available in EP mode, and with TLP Bypass disabled.

Note: The R-tile Avalon Streaming IP for PCIe only provides the PRS capability. To take advantage of this feature, you need to implement the necessary logic in your application.
Note: Only Ports 0 and 1 support PRS.
Table 72.  PRS Interface Signals
Signal Name Direction Description EP/RP/BP Clock
pX_prs_event_valid_i where X = 0, 1, 2, 3 (core number) Input This signal qualifies pX_prs_event_func_i and pX_prs_event_i. There is a single-cycle pulse for each PRS event. EP slow_clk
pX_prs_event_func_i[2:0] where X = 0, 1, 2, 3 (core number) Input The function number for the PRS event. EP slow_clk
pX_prs_event_i[1:0] where X = 0, 1, 2, 3 (core number) Input

00 : Indicate that the function has received a PRG response failure.

01: Indicate that the function has received a response with Unexpected Page Request Group Index.

10: Indicate that the function has completed all previously issued page requests and that it has stopped requests for additional pages. Only valid when the PRS enable bit is clear.

11: reserved.

EP slow_clk

Example Timing Diagram for the PRS Event Interface below shows the timing diagram for the PRS event interface when the application layer of function 0 sends an event of PRG response reception, and the application layer of function 1 sends an event stopping requests for additional pages.

Figure 39. Example Timing Diagram for the PRS Event Interface

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