R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.3.12. SR-IOV VF Error Flag Interface (Endpoint Only)

The VFs, with no AER support, are required to generate Non-Fatal error messages. The IP does not generate any error message. It is up to the user application logic to generate appropriate messages when specific error conditions occur.

The R-tile IP for PCIe makes necessary signals available to the user application logic to generate these messages. The Completion Timeout Interface and the signals listed in the table below provide the necessary information to generate Non-Fatal error messages.

This interface applies to EP only.

Note: Ports 2 and 3 do not support SR-IOV.
Table 74.  RX VF Error Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain

pX_vf_err_poisonedwrreq_s0_o

pX_vf_err_poisonedwrreq_s1_o

where

X = 0, 1 (IP core number)

Output Indicates a Poisoned Write Request is received. EP slow_clk

pX_vf_err_poisonedcompl_s0_o

pX_vf_err_poisonedcompl_s1_o

where

X = 0, 1 (IP core number)

Output Indicates a Poisoned Completion is received. EP slow_clk

pX_vf_err_ur_posted_s0_o

pX_vf_err_ur_posted_s1_o

where

X = 0, 1 (IP core number)

Output Indicates a Posted UR request is received. EP slow_clk

pX_vf_err_ca_postedreq_s0_o

pX_vf_err_ca_postedreq_s1_o

where

X = 0, 1 (IP core number)

Output Indicates a Posted CA request is received. EP slow_clk

pX_vf_err_vf_num_s0_o[10:0]

pX_vf_err_vf_num_s1_o[10:0]

where

X = 0, 1 (IP core number)

Output Indicates the VF number for which the error is detected. EP slow_clk

pX_vf_err_func_num_s0_o[2:0]

pX_vf_err_func_num_s1_o[2:0]

where

X = 0, 1 (IP core number)

Output Indicates the physical function number associated with the VF that has the error. EP slow_clk

pX_vf_err_overflow_o

Output Indicates a VF error FIFO overflow and a loss of an error report. The overflow can happen when coreclkout_hip is slower than the default value. If coreclkout_hip is running at the default frequency, the overflow will not happen. EP slow_clk
Table 75.  TX VF Error Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain

pX_user_sent_vfnonfatalmsg_i

where

X = 0, 1 (IP core number)

Input Indicates the user application sent a non-fatal error message in response to an error detected. EP slow_clk

pX_user_vfnonfatalmsg_vfnum_i[10:0]

where

X = 0, 1 (IP core number)

Input Indicates the VF number for which the error message was generated. This bus is valid when user_sent_vfnonfatalmsg_s0_i is high. EP slow_clk

pX_user_vfnonfatalmsg_func_num_i[2:0]

where

X = 0, 1 (IP core number)

Input Indicates the PF number associated with the VF with the error. This bus is valid when user_sent_vfnonfatalmsg_s0_i is high. EP slow_clk

pX_user_vfnonfatalmsg_ready_o

where

X = 0, 1 (IP core number)

Output

Value 0 indicates an input change is pending. The new value should be held.

pX_user_vfnonfatalmsg_ready_o = 1 when the interface is ready to accept the new value.

EP slow_clk

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