R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

1.2.1. Multifunction and Virtualization Features

The R-tile Avalon® streaming IP for PCI Express* supports the following multifunction and virtualization features:
  • SR-IOV support (Port 0 and Port 1 only).
    Note: Ports 0 and 1 can support 8 PFs and 2K VFs. Ports 2 and 3 do not support SR-IOV, and only support 1 PF.
  • Access Control Service (ACS) capability.
    Note: For ACS, only ports 0 and 1 are supported.
  • Alternative Routing-ID Interpretation (ARI).
  • Function Level Reset (FLR).
    Note: Only Ports 0 and 1 support FLR.
  • TLP Processing Hint (TPH).
    Note: TPH supports the "No Steering Tag (ST)" mode only.
  • Address Translation Services (ATS).
  • Process Address Space ID (PasID).
    Note: Scalable IO and Shared Virtual Memory (SVM) may be available in a future Intel® Quartus® Prime release.
  • Configuration Intercept Interface (CII).
  • Soft VirtIO support.
    Note: VirtIO support for Ports 2 and 3 is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to Intel® Agilex™ FPGAs and SoCs Device Overview.

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