R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

1.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the R-tile Avalon® streaming IP core supports.

Table 6.   Intel® Agilex™ Recommended FPGA Fabric Speed Grades for All Avalon Streaming Widths and Frequencies

Configuration

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Note
Gen5 1x16 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 1x16 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2
Gen3 1x16 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  
Gen5 2x8 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 2x8 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2 3
Gen3 2x8 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  
Gen5 4x4 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 4x4 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2 3
Gen3 4x4 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

PIPE Direct

500 -1, -2  

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® streaming IP core top-level entity (intel_rtile_pcie_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 7.  Resource Utilization Information for the R-tile Avalon® Streaming IP
Link Configuration Device Family ALMs M20Ks Dedicated Logic Registers
Gen5 x16 Intel® Agilex™ 11721 0 32819
Gen4 x16 Intel® Agilex™ 11617 0 28127
Gen3 x16 Intel® Agilex™ 11617 0 28127
16-channel PIPE Direct Intel® Agilex™ 2257 0 1836

For more details on the R-tile Avalon® Streaming design example, refer to R-tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide.

2 -3 devices only support an Application Clock frequency up to 400 MHz.
3 This topology is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

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