R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

6.1. Hardware Debug

Typically, PCI Express link-up involves the following phases:
  1. Link training
  2. BIOS enumeration
  3. Data transfer

The following sections describe the flow to debug issues during the hardware bring-up. Intel recommends a systematic approach to diagnosing issues as illustrated in the following figure.

Figure 54. PCI Express Debug Flow Chart