R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

5.2.3.3. Link Capabilities

Table 89.  Link Capabilities
Parameter Value Default Value Description
Link port number 0 - 255 1 Sets the read-only value of the port number field in the Link Capabilities register.
Slot clock configuration True/False True When this parameter is True, it indicates that the Endpoint uses the same physical reference clock that the system provides on the connector. When it is False, the IP core uses an independent clock regardless of the presence of a reference clock on the connector. This parameter sets the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register. You cannot enable this option when the Enable SRIS Mode option is enabled.

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