R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

A. Configuration Space Registers

To access the configuration space registers of the PFs and VFs in the R-tile Avalon® Streaming IP for PCI Express, drive the base addresses for the appropriate PFs/VFs using the pX_hip_reconfig_address_i[31:0] bus in the Hard IP Reconfiguration Interface. For more details, refer to Hard IP Reconfiguration Interface.

The register maps for the R-tile Avalon® Streaming IP for PCI Express Revision A in X16, X8 and X4 modes can be found at R-Tile Avalon Streaming Intel FPGA IP for PCI Express Revision A Configuration Register Maps.

The register maps for the R-tile Avalon® Streaming IP for PCI Express Revision B in X16, X8 and X4 modes can be found at R-Tile Avalon Streaming Intel FPGA IP for PCI Express Revision B Configuration Register Maps.

For more details, refer to PCI Express Base Specification Revision 5.0, Version 1.0.

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