R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/07/2022
Public
Document Table of Contents

4.4.4.1. MAC to PHY (M2P) Signals

Table 82.  PIPE Direct EMIB Control Deskew Channel - M2P Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_deskew_clear_0/1/2/3_i Input When asserted, the current tx_dsk_eval_done and tx_dsk_status are cleared. A new deskew evaluation is expected after the current status is cleared. This signal is asserted for two clock cycles. pipe_direct_pld_tx_clk_out_o

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