R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022

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4.3.8. Power Management Interface

Software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management output signals indicate the current power state. The IP core supports the two mandatory power states: D0 (full power) and D3Hot. It does not support the optional D1 and D2 low-power states.

The correspondence between the device power states (D states) and link power states (L states) is as follows:

Table 67.  Relationship Between Device and Link Power States
Device Power State Link Power State
D0 L0
D1 (not supported) L1
D2 (not supported) L1
D3Hot L1, L2/L3 Ready
D3Cold L2, L3

The following table shows the support for L2/L3 states in R-tile.

Table 68.  L2/L3 Support in R-tile
L2/L3 entry Ok Ok
L2 exit Host to initiate or Cold Reset Cold Reset
L3 exit Cold Reset Cold Reset
Note: The R-tile Avalon® Streaming IP for PCIe only supports ASPM L1 in devices with the suffix R2 or R3 in their OPN number. For additional details, refer to Intel® Agilex™ FPGAs and SoCs Device Overview.
Table 69.  Power Management Interface
Signal Name Direction Description Clock Domain EP/RP/BP
pm_curnt_state_o[7:0] O Indicates the current power state.
  • 8'b00000001 : L0 or IDLE
  • 8'b00000010 : L0s
  • 8'b00000100 : L1
  • 8'b00001000 : L2
  • 8'b00010000 : L3
  • Other values are invalid.
Async EP/RP/BP

x16/x8: pm_dstate_o[31:0]

x4: pm_dstate_o[3:0]

O Power management D-state for each function.
  • 4'b0001 : D0
  • 4'b1000 : D3 Hot
  • Other values are invalid.
Async EP/RP/BP

x16/x8: apps_pm_xmt_pme_i[7:0]

x4: NA

I The application logic asserts this signal for one cycle to wake up the Power Management Capability (PMC) state machine from a D1, D2, or D3 Hot power state. Upon wake-up, the IP core sends a PM_PME message. This signal needs to be asserted for one clock cycle. slow_clk EP/BP

x16/x8: apps_ready_entr_l23_i

x4: NA

I The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. The app_ready_entr_l23_i signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready). The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active. This is a level-sensitive signal. slow_clk EP/BP
apps_pm_xmt_turnoff_i I This signal is a pulse input. It is a request from the Application Layer to generate a PM_Turn_Off message. The Application Layer must assert this signal for one clock cycle. The IP core does not return an acknowledgement or grant signal. The Application Layer must not pulse the same signal again until the previous message has been transmitted. slow_clk RP
app_init_rst_i I The Application Layer uses this signal to request a hot reset to downstream devices. The hot reset request will be sent when a single-cycle pulse (~20ns) is applied to this pin. Asynchronous RP
app_req_retry_en_i[7:0] I

When asserted, the PCIe Hard IP responds to Configuration TLPs with a CRS (Configuration Retry Status) if it has not already responded to a Configuration TLP with non-CRS status since the last reset. The user application can use this signal to hold off on enumeration. This input is not used for Root Ports.

This bus applies to both Endpoints when the Hard IP is configured as 2x8.

The x4 cores (Ports 2 and 3) also have these pins but they are not used and need to be driven to zero.

Asynchronous EP
app_xfer_pending_i I This signal prevents the entry to L1 or initiates the exit from L1. Asynchronous EP/RP/BP

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