R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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2.3.2. Reset

Follow the guidelines below for a proper reset implementation for the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express:
  • There is only one PERST# (pin_perst_n) pin on R-tile. Therefore, toggling pin_perst_n will affect the entire R-tile. If the R-tile is configured using Configuration Mode 1 or Configuration Mode 2, toggling pin_perst_n will affect all the active cores. For more information on the Configuration Modes, refer to Configuration Modes Supported by the R-tile Avalon Streaming IP for PCI Express.
  • pin_perst_n is a "power good" indicator from the associated power domain (to which R-tile is connected). Also, it shall qualify that both the R-tile refclk0 and refclk1 are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
  • pin_perst_n assertion is required for the Autonomous mode functionality in the R-tile Avalon® Streaming Intel® FPGA IP for PCIe. In Autonomous mode (enabled by default), the IP can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and will send out Completion TLPs with the Configuration Retry Status (CRS) set until the FPGA fabric is configured and ready.
  • To prevent potential device degradation, the pin_perst_n signal must not be held active if power is supplied to the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express when the FPGA is in user mode. If the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express is planned to be used but not in the early phases of your design cycle, you must configure it in BTI mode using the following qsf assignment:

    set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

  • pin_perst_n assertion should be avoided during a functional-level reset or before a functional-level reset is completed since this could impact the link training process. In case this occurs, a cold reset would be required to properly complete the link training process.
  • The pX_reset_status_n_o signal from the R-tile Avalon® Streaming Intel FPGA IP for PCI Express includes an accumulative characteristic related to the number of back-to-back pin_perst_n assertions. Each back-to-back pin_perst_n event will be queued and executed one after the other, affecting the total time it takes for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express to come out of reset and deassert the pX_reset_status_n_o signal. For additional information on the pX_reset_status_n_o signal, refer to Resets.

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