R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.4.7. PIPE Lane Reset Staggering

This section focuses on the staggering for the lane resets of the R-tile Avalon Streaming IP. These lane resets are driven by a Soft IP controller. The IP controller executes a part of the reset procedure for the R-tile Avalon Streaming IP. It only performs the lane reset procedure when the Soft IP itself is out of reset. Each lane has its own lnX_pipe_direct_pld_pcs_rst_n_i driven by the Soft IP controller. When multiple Soft IP controllers are being implemented, each Soft IP can reset its respective lane independent of the other Soft IPs.

Reset staggering is optional. The staggering is to reduce the power distribution network (PDN) noise during power-up. If implemented, the reset staggering should start after lnX_pipe_direct_tx_transfer_en is asserted.

The staggering interval must be set to more than 100ns. The lane resets are staggered in such a way that they start from lane 0 to lane 15 for the PIPE Direct x16 mode and lane0 to lane 7 for any PIPE Direct bundle mode. Both reset assertion and deassertion must be staggered.

The lnX_pipe_direct_powerdown_i and lnX_pipe_direct_rxstandby_i signals also require lane staggering per bundle. The staggering must be greater or equal to a x4 bundle. For example, in the PIPE Direct 8x2 bundle mode, the lane staggering for the mentioned PIPE signals must be grouped in x4 or greater.

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