R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.2. Serial Data Interface

In PCI Express modes, R-tile natively supports 4, 8, or 16 PCIe lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes. The number of lanes will be different based on the topology which indicates how many lanes are used.

In PIPE Direct mode, R-tile supports 16 PIPE Direct lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes. The number of lanes will be different based on the topology which indicates how many lanes are used.
Table 47.  Serial Data Interface
Name Direction Description

tx_p_out[15:0]

tx_n_out[15:0]

Output

Transmit serial data outputs using the High Speed Differential I/O standard.

rx_p_in[15:0]

rx_n_in[15:0]

Input

Receive serial data inputs using the High Speed Differential I/O standard.

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