R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3. PCI Express Mode

In PCI Express mode, only the PCI Express controller stack is active. The four PCI Express cores (x16, x8, x4_0 and x4_1) interface with the application logic in the FPGA fabric via Avalon® streaming interfaces. You can determine which core each interface in this section belongs to by looking at the prefixes in the signal names:
  • p0 : x16 core
  • p1 : x8 core
  • p2 : x4_0 core
  • p3 : x4_1 core
Note: The x4_0 core is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

R-tile Top-Level Block Diagram in PCI Express Mode below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefixes pn (where n = 0, 1, 2 or 3) depending on which of the supported topologies (x16, x8x8, x4x4x4x4) the R-tile Avalon® streaming IP for PCIe is in.

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like clocks and resets.

Figure 23. R-tile Top-Level Block Diagram in PCI Express Mode

pX: X is port number, ranges from 0 to 3.

st#: # is segment number, ranges from 0 to 3.