R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.20 22.2 6.0.0

Updated the Debug Toolkit section to document the additional capabilities for users to verify in hardware the status of the R-tile Avalon® Streaming Intel FPGA IP for PCI Express.

Documented the new ports pX_cold_perst_n_i, pX_warm_perst_n_i, and pX_ip_rst_n_o.

Updated the Independent PERST section with new timing diagrams showing the behaviors of the pX_cold_perst_n_i and pX_warm_perst_n_i signals.

Updated the Hard IP Reconfiguration Interface section with a new timing diagram showing the behavior of the signals on this interface while doing a read of the configuration space registers.

2022.03.28 22.1 5.0.0

Removed Questa* FPGA Edition from the list of supported simulators in the Features section.

Updated the FPGA fabric speed grades table in the Performance and Resource Utilization section.

Updated the application clock frequencies table in the Clocking section.

Updated the list of PCI Express Capability Structure registers that need to be implemented in the Application logic in the Hard IP Reconfiguration Interface.

Updated the tables in the Completion Buffer Size section.

Added the subsections D3Hot Exit Initiated by Host, D3Hot Exit Initiated by EP, D3Cold Entry and D3Cold Exit to the Power Management Interface section.

Modified the list of steps given in the PIPE Direct Reset Sequence section.

Modified the description given in the PIPE Direct Speed Change section.

2021.12.13 21.4 4.0.0

Added the new section BTI Protection Mode.

Updated the Completion Buffer Size section to show the correct buffer sizes. Also added examples showing the amount of Completion buffer entries consumed for Memory Read requests. Finally, added a suggested flow for the Application logic to track the completion buffer entries and based on this, schedule Non-Posted (NP) requests to the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express.

Updated the text descriptions and timing waveforms for the Avalon Streaming RX Interface and the Avalon Streaming TX Interface to show how the user application logic can properly use these interfaces.

Updated the signal descriptions and timing waveforms for the Deskew Channel section to show how the user application logic can properly use this interface.

2021.10.06 21.3 3.0.0 Removed the section ECRC due to missing information on the register offsets for the ECRC or LCRC counters.
2021.10.04 21.3 3.0.0

Updated the block diagrams in the PCI Express Mode and PIPE Direct Mode sections to match the interface signals on the 21.3 block symbol for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express.

Added a Note to the Avalon Streaming TX Interface section stating that for this interface, the SOP can only be sent on segments 0 and 2.

Added the Root Port Enumeration Appendix chapter.

2021.07.12 21.2 2.0.0 Initial release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message