R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.4.6. PIPE Direct Speed Change

In the PIPE Direct Data mode, the clock for the RX datapath is sourced from the PHY recovered clock (pipe_direct_pld_rx_clk_out_o). The PHY recovered clock changes frequency when the PHY trains from Gen1 to Gen5. During the PIPE Direct RX rate change, the following sequence needs to be adhered to.

The soft IP controller first changes the rate or width if required. The R-tile Avalon Streaming IP only asserts lnX_pipe_direct_pclkchangeok_o after the Soft IP controller has made the changes. The Soft IP controller asserts lnX_pipe_direct_pclkchangeack_i when the change is complete and stable. After the Soft IP controller asserts lnX_pipe_direct_pclkchangeack_i, the R-tile Avalon Streaming IP responds by asserting lnX_pipe_direct_phystatus_o for one cycle and deasserting lnX_pipe_direct_pclkchangeok_o at the same time as lnX_pipe_direct_phystatus_o. The Soft IP controller deasserts lnX_pipe_direct_pclkchangeack_i when lnX_pipe_direct_pclkchangeok_o is sampled low.

As a reference, the following diagram illustrates the speed change from Gen1 to Gen5.
Note: Although the diagram below illustrates a speed change from Gen1 to Gen5, the overall sequence applies to all speed changes. However, the final value of ln0_pipe_direct_rate_i varies depending on what the final speed is.
Figure 44. PIPE Direct Speed Change

Below are the steps required for the speed change sequence for lane 0 in the R-Tile Avalon Streaming IP when configured in PIPE Direct mode. This behavior also applies to other lanes and other speed rates.

Note that each of the steps required correlates with the corresponding letter in the waveforms.

  • Steps (a, b, c, d): The Soft IP controller stops the data transmission on the TX data path signals in preparation for the speed change event.
  • Step (e): Once ready, the Soft IP Controller will set the targeted rate on the ln0_pipe_direct_rate_i signal.
  • Steps (f, g, h): The ln_pipe_direct_reset_status_n_o signal goes low, invalidating any further data received on the ln0_pipe_direct_rxdata_o bus. Additionally, the ln0_cdrlock2data_o signal goes low.
    Note: The Rx data must be qualified with an AND operation between the corresponding ln_pipe_direct_reset_status_n_o lane signal, ln0_pipe_direct_rxdatavalid0_o and ln0_pipe_direct_rxdatavalid1_o.
  • Steps (i,j): The ln0_pipe_direct_rxdatavalid0_o and ln0_pipe_direct_rxdatavalid1_o signal go low.
    Note: The Rx data must be qualified with an AND operation between the corresponding ln_pipe_direct_reset_status_n_o lane signal, ln0_pipe_direct_rxdatavalid0_o and ln0_pipe_direct_rxdatavalid1_o.
  • Step (k): The ln0_pipe_direct_pld_rx_clk_out_o stops toggling.
  • Steps (l, m): The R-Tile Avalon Streaming IP asserts ln0_pipe_direct_pclkchangeok_o and the Soft IP Controller confirms by driving high the ln0_pipe_direct_pclkchangeack_i signal.
  • Step (n): The ln0_pipe_direct_cdrlockstatus_o signal goes low until the R-Tile Avalon Streaming IP locks to the new clock frequency.
  • Step (o): The ln0_pipe_direct_cdrlockstatus_o signal goes high once the R-Tile Avalon Streaming IP locks to the new clock frequency.
  • Steps (p, q): The R-Tile Avalon Streaming IP confirms a successful rate change with a single pulse on the ln0_pipe_direct_phystatus_o signal and by driving low the ln0_pipe_direct_pclkchangeok_o signal.
  • Step (r): The Soft IP Controller acknowledges the rate change by driving low the ln0_pipe_direct_pclkchangeack_i signal.
  • Steps (s, t, u, v): The Soft IP Controller starts the data transmission at the new rate on the TX data path signals.
  • Steps (w, x, y): The ln0_cdrlock2data_o signal is driven high by the R-Tile Avalon Streaming IP. The ln0_pipe_direct_rxdatavalid0_o and the ln0_pipe_direct_rxdatavalid1_o signals go high.
    Note: The RX data is not valid until the corresponding ln_pipe_direct_reset_status_n_o lane signal goes high.
  • Step (z): The corresponding ln_pipe_direct_reset_status_n_o lane signal goes high. This qualifies the RX data along with the ln0_pipe_direct_rxdatavalid0_o and ln0_pipe_direct_rxdatavalid1_o signals.

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