R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.6. IP Core Support Levels

The following table shows the support levels of the R-tile Avalon® streaming IP core in Intel® Agilex™ devices.

Table 8.  R-tile Avalon streaming IP for PCIe Support Matrix for Intel® Agilex™ DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support
EP RP BP UP/DN
16-channel PIPE Direct N/A N/A N/A
Gen5 x16 1024-bit SCTH SCTH SCTH
Gen4 x16 1024-bit SCTH SCTH SCTH
Gen3 x16 1024-bit SCTH SCTH SCTH
Gen4 x16 512-bit 2 SCTH SCTH SCTH
Gen3 x16 512-bit 2 SCTH SCTH SCTH
Gen5 x8/x8 512-bit SCTH SCTH SCTH
Gen4 x8/x8 512-bit SCTH SCTH SCTH
Gen3 x8/x8 512-bit SCTH SCTH SCTH
Gen4 x8/x8 256-bit 2 SCTH SCTH SCTH
Gen3 x8/x8 256-bit 2 SCTH SCTH SCTH
Gen5 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen4 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen3 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen4 x4/x4/x4/x4 128-bit 2 SCTH SCTH SCTH
Gen3 x4/x4/x4/x4 128-bit 2 SCTH SCTH SCTH
Note: PIO design examples are available only in the x16 and 2x8 EP modes in the 22.2 release of Intel® Quartus® Prime. For additional details, refer to R-tile Avalon® Streaming Intel FPGA IP for PCI Express* Design Example User Guide.
2 These configurations are only available in devices with the suffix R2 in their OPN number. For more details on OPN decoding, refer to Intel® Agilex™ FPGAs and SoCs Device Overview.

Did you find the information on this page useful?

Characters remaining:

Feedback Message