R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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3.2.1.3. VF to PF Mapping

VF to PF mapping always starts from the lowest possible PF number. For instance, if the IP has 2 PFs, wherein PF0 has 64 VFs and PF1 has 16 VFs, VF1 to VF64 are mapped to PF0, and VF65 to VF80 are mapped to PF1.

Currently, the IP core only supports the following PF/VF combinations:
Table 15.  Supported PF/VF Combinations
Number of PFs Number of VFs per PF (PF0/PF1/PF2/PF3/PF4/PF5/PF6/PF7) Total VFs
1 8 8
1 16 16
1 32 32
1 64 64
1 128 128
1 256 256
1 512 512
2 16/16 32
2 32/32 64
2 128/128 256
2 256/256 512
2 32/0 32
2 0/32 32
2 64/0 64
2 0/64 64
2 128/0 128
2 0/128 128
2 256/0 256
2 0/256 256
2 512/0 512
2 0/512 512
2 1024/0 1024
2 0/1024 1024
2 2048/0 2048
2 0/2048 2048
4 128/0/0/0 128
4 0/128/0/0 128
4 256/0/0/0 256
4 0/256/0/0 256
4 1024/0/0/0/0 1024
4 0/1024/0/0 1024
8 256/0/0/0/0/0/0/0 256
8 0/256/0/0/0/0/0/0 256

For example, the row that shows the combination of four PFs, 256 VFs, and the notation 256/0/0/0 in the Number of VFs per PF column indicates that all 256 VFs are mapped to PF0, while no VF is mapped to PF1, PF2 or PF3.

Note:

SR-IOV permutations allow any PF to be assigned the initial VF allocation.

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