R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.3.1.2.5. TX Flow Control Interface

Before a TLP can be transmitted, flow control logic verifies that the link partner's RX port has sufficient buffer space to accept it. The TX Flow Control interface reports the link partner's available RX buffer space to the Application. It reports the space available in units called Flow Control credits for posted, non-posted and completion TLPs (as defined in the RX Flow Control Interface section).

For more information on how credit control in general is implemented in this IP, refer to Credit Control.

Table 53.  TX Flow Control Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_tx_st_hcrdt_update_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Indicates credit is made available for the different types of Header.

Each Header (including the TLP Prefix, if any) consumes one credit.

[0] : Posted Header (PH)

[1] : Non-Posted Header (NPH)

[2] : Completion Header (CPLH)

When the link partner advertises infinite credits, this signal will get asserted for one clock cycle, with a value of 0 on pX_tx_st_hcrdt_update_cnt_o during the credit initialization phase.

EP/RP/BP coreclkout_hip
pX_tx_st_hcrdt_update_cnt_o[5:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Indicates number of credits released.

[1:0] : number of PH credits released

[3:2] : number of NPH credits released

[5:4] : number of CPLH credits released

Valid when the corresponding pX_tx_st_hcrdt_update_o bit = 1.

The maximum number of credits released is three.

When the link partner advertises infinite credits, this signal will reflect a 0 during the credit initialization phase (when pX_tx_st_hcrdt_update_o is asserted for one clock cycle).

EP/RP/BP coreclkout_hip
pX_tx_st_hcrdt_init_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Credit Initialization indicator. These signals remain high for entire initialization phase. A High to Low transition indicates the completion of the credit initialization phase.

[0] : PH

[1] : NPH

[2] : CPLH

EP/RP/BP coreclkout_hip
pX_tx_st_hcrdt_init_ack_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates the Application logic is ready for the credit initialization phase

[0] : PH

[1] : NPH

[2] : CPLH

EP/RP/BP coreclkout_hip
pX_tx_st_dcrdt_update_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Indicates credit is made available for the different types of Data.

[0] : Posted Data (PD)

[1] : Non-Posted Data (NPD)

[2] : Completion Data (CPLD)

When the link partner advertises infinite credits, this signal will get asserted for one clock cycle, with a value of 0 on pX_tx_st_dcrdt_update_cnt_o during the credit initialization phase.

EP/RP/BP coreclkout_hip
pX_tx_st_dcrdt_update_cnt_o[11:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Indicates number of credits released.

[3:0] : number of PD credits released

[7:4] : number of NPD credits released

[11:8] : number of CPLD credits released

Valid when the corresponding pX_tx_st_dcrdt_update_o bit = 1.

The maximum number of credits released is 15.

When the link partner advertises infinite credits, this signal will reflect a 0 during the credit initialization phase (when pX_tx_st_dcrdt_update_o is asserted for one clock cycle.

EP/RP/BP coreclkout_hip
pX_tx_st_dcrdt_init_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Credit Initialization indicator. These signals remain high for entire initialization phase. A High to Low transition indicates the completion of the credit initialization phase.

[0] : PD

[1] : NPD

[2] : CPLD

EP/RP/BP coreclkout_hip
pX_tx_st_dcrdt_init_ack_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates the Application logic is ready for the credit initialization phase

[0] : PD

[1] : NPD

[2] : CPLD

EP/RP/BP coreclkout_hip

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