R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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2.3.2.2.1. REFCLK and PERST Guidelines when Using Independent PERST

  • In Configuration Mode 0 (1x16), the independent PERST and independent REFCLK are available with:
    • The clock coming from a single source connected to refclk0 and refclk1.
    • The reset coming from pin_perst_n.
  • In Configuration Mode 1 (2x8), the independent PERST and REFCLK are conditional with:
    • Port 0 (P0):
      • The clock source comes from refclk0.
      • The reset source can come from pin_perst_n, p0_cold_perst_n_i or p0_warm_perst_n_i.
    • Port 1 (P1):
      • The clock source comes from refclk1.
      • The reset source can come from pin_perst_n, p1_cold_perst_n_i or p1_warm_perst_n_i.
    • Both refclk0 and refclk1 need to be always active.
    • As stated in the Independent PERST section, pin_perst_n has the highest priority for reset over pX_cold_perst_n_i or pX_warm_perst_n_i, and toggling pin_perst_n affects all the ports.
  • In Configuration Mode 2 (4x4), the independent PERST feature is available, but REFCLKs are not independent.
    • Port 0 (P0):
      • The clock source comes from refclk0.
      • The reset can come from pin_perst_n, p0_cold_perst_n_i or p0_warm_perst_n_i.
    • Port 1 (P1):
      • The clock source comes from refclk1.
      • The reset can come from pin_perst_n, p1_cold_perst_n_i or p1_warm_perst_n_i.
    • Port 2 (P2):
      • The clock source comes from refclk0.
      • The reset can come from pin_perst_n, p2_cold_perst_n_i or p2_warm_perst_n_i.
    • Port 3 (P3):
      • The clock source comes from refclk1.
      • The reset can come from pin_perst_n, p3_cold_perst_n_i or p3_warm_perst_n_i.
    • Both refclk0 and refclk1 need to be always active.
    • As stated in the Independent PERST section, pin_perst_n has the highest priority for reset over pX_cold_perst_n_i or pX_warm_perst_n_i, and toggling pin_perst_n affects all the ports.