R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.3.1. Avalon® Streaming Interface

Each of the PCIe cores has its own Avalon® streaming interface to the user logic in the FPGA fabric. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the topologies:
Table 48.  IP to FPGA Fabric Interfaces Summary
Topology Avalon-ST Interface Count Data Width (each Interface) Header Width (each Interface) TLP Prefix Width (each Interface) Application Clock Frequency Note
Gen5 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

Gen3 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen5 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
256-bit (one 256-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen3 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
256-bit (one 256-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

250 MHz / 275 MHz / 300 MHz

3
Gen5 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
128-bit (one 128-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen3 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
128-bit (one 128-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

250 MHz / 275 MHz / 300 MHz

3

The R-tile PCIe Hard IP provides an Avalon® Streaming-like interface with separate header and data to improve the bandwidth utilization.

The Avalon® Streaming interface has different data bus widths depending on the link width configuration of the PCIe IP.

Table 49.   Avalon® Streaming Interface Data and Header Bus Widths per Port
Link Width Link Speed Data Width (Bits) Header Width (Bits) TLP Prefix Width (Bits) Note
x16 Gen5 1024 (4 x 256) 512 (4 x 128) 128 (4 x 32)  
Gen4 1024 (4 x 256) 512 (4 x 128) 128 (4 x 32)  
512 (2 x 256) 256 (2 x 128) 64 (2 x 32)
Gen3 1024 (4 x 256) 512 (4 x 128) 128 (4 x 32)  
512 (2 x 256) 256 (2 x 128) 64 (2 x 32) 4
x8 Gen5 512 (2 x 256) 256 (2 x 128) 64 (2 x 32)  
Gen4 512 (2 x 256) 256 (2 x 128) 64 (2 x 32)  
256 (1 x 256) 128 (1 x 128) 32 (1 x 32) 4
Gen3 512 (2 x 256) 256 (2 x 128) 64 (2 x 32)  
256 (1 x 256) 128 (1 x 128) 32 (1 x 32) 4
x4 Gen5 256 (2 x 128) 256 (2 x 128) 64 (2 x 32)  
Gen4 256 (2 x 128) 256 (2 x 128) 64 (2 x 32)  
128 (1 x 128) 128 (1 x 128) 32 (1 x 32) 4
Gen3 256 (2 x 128) 256 (2 x 128) 64 (2 x 32)  
128 (1 x 128) 128 (1 x 128) 32 (1 x 32) 4
3 This topology is only available in devices with the suffix R2 or R3 in their OPN number. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.
4 This topology is only available in devices with the suffix R2 or R3 in their OPN number. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

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