R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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6.2.4.3. Configuration Space

This tab allows you to read the configuration space registers directly, without the need to issue a Configuration Read from the link partner. Depending on the Hard IP Mode selected during the IP configuration (for example Gen5 2x8), you will see a separate tab with the configuration space for each port. Also, please note that:
  • All the information is read-only.
  • The per-lane information under the tab Configuration Space corresponds to the logical lanes.
  • Use the Refresh Configuration Space button to read the Configuration Space registers.
Figure 56. Configuration Space Tab

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