R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

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4.4.4.2. PHY to MAC (P2M) Signals

Table 82.  PIPE Direct EMIB Control Deskew Channel P2M Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_txdeskewmarker_i Input Tx Deskew marker used to deskew EMIB routings per bundle mode. This is a simple repeating pulse that provides a protocol-agnostic mechanism to detect EMIB channel skew and perform alignment. The marker fans out and appears on all bundle channels simultaneously once every 16 clock cycles. The deskew module looks for the deskew marker from each EMIB channel and adds delays on the early channels to compensate for the delays of the late channels. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_active_chans_o Output Indicates which channels received a deskew marker. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_o Output

Value is latched upon an error, and held until the state machine is restarted via i_dsk_clear or async reset.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_status_[3:0]_o Output

Indicates a deskew monitor error.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_status_[3:0]_o Output

Indicates the deskew evaluation result.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

Note: octet#_pipe_direct_phy_dsk_status should be monitored only after octet#_pipe_direct_phy_dsk_valid is asserted.
pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_valid_[3:0]_o Output

Indicates the deskew operation status.

When using x16, the octet#_pipe_direct_phy_dsk_valid_o from each of the octets must be ANDed together by the user logic.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o Output Indicates the deskew process is complete. This signal is for debugging purpose. When using x16, the octet#_pipe_direct_phy_dsk_eval_done_o from each of the octets must be ANDed together by the user logic. pipe_direct_pld_tx_clk_out_o
To use the deskew interface, follow these steps:
  1. The controller in the application logic sends the deskew marker for each lane of the bundle every 16 pipe_direct_pld_tx_clk_out_o clock cycles using the signal ln*_pipe_direct_txdeskewmarker_i.
  2. After the data from the EMIB is deskewed, octet*_pipe_direct_phy_dsk_valid_o is asserted, indicating deskew done status.
    Note: (*) When using x16, the octet*_pipe_direct_phy_dsk_valid_o from each of the octets must be ANDed together.
  3. In addition to the octet*_pipe_direct_phy_dsk_valid_o signals, the PIPE interface provides octet*_pipe_direct_phy_dsk_eval_done_o and octet*_pipe_direct_phy_dsk_status_*_o signals to show the details of the deskew status.
    Note: (#) These signals are for debugging purposes only. The user application logic should rely only on the octet*_pipe_direct_phy_dsk_valid_o signals.
  4. The octet*_pipe_direct_deskew_clear_i signals on both octets can be used to clear the current deskew state to allow additional deskew evaluations. When using x16, the octet*_pipe_direct_deskew_clear_i for each of the octets must be used.
  5. After the pulse on octet*_pipe_direct_deskew_clear_i, the deskew state on octet*_pipe_direct_phy_dsk_monitor_err_o bus is cleared.

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