R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.2.1. Single PERST

The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and Soc) is powered up first. The R-tile refclk0 is fed by the on-board free-running oscillator and the refclk1 driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.

Figure 5. Single PERST# Connection in Bifurcated 2x8 Mode

Did you find the information on this page useful?

Characters remaining:

Feedback Message