R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.8. Unused Lanes in PIPE Direct Mode

In PIPE Direct mode, the Soft IP controller is responsible for driving the lnX_pipe_direct_powerdown_i[1:0] to 2’b11 in the FPGA core fabric for those unused lanes. Upon entering user mode followed by the deassertion of ln0_pipe_direct_pld_pcs_rst_n_i by the Soft IP controller, the unused lanes will transition to P2 pstate.

Did you find the information on this page useful?

Characters remaining:

Feedback Message