Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
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2.5.5. Placement Settings for the Intel® Stratix® 10 10GBASE-KR PHY IP Core

The Intel® Quartus® Prime Pro Edition software provides the options to specify design partitions or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your full design.

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