Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 1/29/2021
Public
Document Table of Contents
Document Table of Contents
1. Datasheet 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Intel® Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. Datasheet
1.1. Intel® Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Intel® Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Intel® Stratix® 10 10GBASE-KR PHY IP Core
5. Intel® Stratix® 10 10GBASE-KR PHY Registers
5.1. Register Map 5.2. Register Definitions
6. Interface Signals
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Intel® Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Intel® Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview
8.1.1. Features
1. Datasheet
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Intel® Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants
B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

2.5.5. Placement Settings for the Intel® Stratix® 10 10GBASE-KR PHY IP Core

The Intel® Quartus® Prime Pro Edition software provides the options to specify design partitions or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your full design.

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