Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

7.2.3. Design Example Interface Signals

The Intel® Stratix® 10 10GBASE-KR testbench is self-contained and does not require you to drive any input signals.

Table 22.   Intel® Stratix® 10 10GBASE-KR Hardware Design Example Interface Signals
Signal Direction Description
pll_refclk Input Transceiver reference clock. Drive at 644.53125 or 322.255626 MHz.
clk50 Input System clock input. Drive at 50 MHz. The intent is to drive this from a 50 MHz oscillator on the board.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
user_pb[7:0] Input User push buttons. The hardware design example connects these bits to drive push buttons on the target board.
ch0_rx_serial_data Input Channel 0 Transceiver PHY input serial data.
ch1_rx_serial_data Input Channel 1 Transceiver PHY input serial data.
ch0_tx_serial_data Output Channel 0 Transceiver PHY output serial data.
ch1_tx_serial_data Output Channel 1 Transceiver PHY output serial data.
user_led[7:0] Output Status signals. The hardware design example connects these bits to drive LEDs on the target board.

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