Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021

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Document Table of Contents

7.1.7. Testing the Hardware Design Example

After you compile the Intel® Stratix® 10 10GBASE-KR PHY IP core design example and configure it on your Intel® Stratix® 10 GX device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these steps:
  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hardware_test_design to change directory to <design_example_dir>/hardware_test_design.
  3. Type source console.tcl to open a connection to the JTAG master.
You can program the IP core with the following design example commands:
  • loop_on: Turns on internal serial loopback.
  • loop_off: Turns off internal serial loopback.
  • reconfig_read <channel> <addr> : Returns the IP core register value at <channel> and <addr>.
  • reconfig_write <channel> <addr> <data> : Writes <data> to the IP core register at <channel> and <addr>.
  • rst <channel> : Reset the instance of KR IP.
  • dis_max_wait_timer: Disables the link training max wait timer.
  • dis_nonce: Ignores nonce during AN. This allows AN to work if channel is looped back to itself.
  • rd_seq_stat: Display status from sequencer block.
  • rd_an_stat: Display status back from AN block.
  • rd_lt_stat: Display status back from LT block.